mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 12:59:43 +09:00
691d719db7
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 Toradex
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <micrel.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/* rom_pointer[1] contains the size of TEE occupies */
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if (rom_pointer[1])
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gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
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else
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#if IS_ENABLED(CONFIG_FEC_MXC)
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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int tmp;
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switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
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case PHY_ID_KSZ9031:
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/*
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* The PHY adds 1.2ns for the RXC and 0ns for TXC clock by
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* default. The MAC and the layout don't add a skew between
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* clock and data.
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* Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for
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* the TXC path to get the required clock skews.
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*/
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/* control data pad skew - devaddr = 0x02, register = 0x04 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x0070);
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/* rx data pad skew - devaddr = 0x02, register = 0x05 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x7777);
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/* tx data pad skew - devaddr = 0x02, register = 0x06 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x0000);
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/* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC,
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0x03f4);
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break;
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case PHY_ID_KSZ9131:
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default:
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/* read rxc dll control - devaddr = 0x2, register = 0x4c */
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tmp = ksz9031_phy_extended_read(phydev, 0x02,
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MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
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MII_KSZ9031_MOD_DATA_NO_POST_INC);
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/* disable rxdll bypass (enable 2ns skew delay on RXC) */
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tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
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/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
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tmp = ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
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/* read txc dll control - devaddr = 0x02, register = 0x4d */
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tmp = ksz9031_phy_extended_read(phydev, 0x02,
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MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
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MII_KSZ9031_MOD_DATA_NO_POST_INC);
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/* disable txdll bypass (enable 2ns skew delay on TXC) */
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tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
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/* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
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tmp = ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, tmp);
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break;
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}
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC))
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setup_fec();
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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return 0;
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}
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#endif
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