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https://github.com/brain-hackers/u-boot-brain
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384980c687
x86 GPIO registers are accessed via I/O port whose base address is configured in a PCI configuration register on the PCH device. Add an op get_gpio_base to get the GPIO base address from PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
64 lines
1.2 KiB
C
64 lines
1.2 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <pch.h>
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#include <dm/root.h>
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DECLARE_GLOBAL_DATA_PTR;
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int pch_get_spi_base(struct udevice *dev, ulong *sbasep)
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{
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struct pch_ops *ops = pch_get_ops(dev);
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*sbasep = 0;
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if (!ops->get_spi_base)
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return -ENOSYS;
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return ops->get_spi_base(dev, sbasep);
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}
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int pch_set_spi_protect(struct udevice *dev, bool protect)
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{
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struct pch_ops *ops = pch_get_ops(dev);
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if (!ops->set_spi_protect)
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return -ENOSYS;
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return ops->set_spi_protect(dev, protect);
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}
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int pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
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{
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struct pch_ops *ops = pch_get_ops(dev);
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*gbasep = 0;
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if (!ops->get_gpio_base)
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return -ENOSYS;
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return ops->get_gpio_base(dev, gbasep);
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}
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static int pch_uclass_post_bind(struct udevice *bus)
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{
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/*
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* Scan the device tree for devices
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*
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* Before relocation, only bind devices marked for pre-relocation
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* use.
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*/
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return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
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gd->flags & GD_FLG_RELOC ? false : true);
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}
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UCLASS_DRIVER(pch) = {
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.id = UCLASS_PCH,
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.name = "pch",
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.post_bind = pch_uclass_post_bind,
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};
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