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![Simon Glass](/assets/img/avatar_default.png)
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
221 lines
5.2 KiB
C
221 lines
5.2 KiB
C
/*
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* (C) Copyright 2003-2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* modified for Promess PRO - by Andy Joseph, andy@promessdev.com
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* modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
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* modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
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* Also changed the refresh for 100MHz operation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#if defined(CONFIG_STATUS_LED)
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#include <status_led.h>
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#endif /* CONFIG_STATUS_LED */
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/* Kollmorgen DPR initialization data */
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struct init_elem {
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unsigned long addr;
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unsigned len;
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char *data;
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} init_seq[] = {
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{0x500003F2, 2, "\x86\x00"}, /* HW parameter */
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{0x500003F0, 2, "\x00\x00"},
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{0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */
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};
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/*
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* Initialize Kollmorgen DPR
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*/
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static void kollmorgen_init(void)
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{
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unsigned i, j;
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vu_char *p;
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for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
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p = (vu_char *)init_seq[i].addr;
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for (j = 0; j < init_seq[i].len; ++j)
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*(p + j) = *(init_seq[i].data + j);
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}
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printf("DPR: Kollmorgen DPR initialized\n");
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}
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/*
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* Early board initalization.
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*/
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int board_early_init_r(void)
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{
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/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
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*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
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/* Initialize Kollmorgen DPR */
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kollmorgen_init();
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return 0;
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}
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/*
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* Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
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* PHY goes into FX mode. To take it out of the FX mode and switch into
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* desired TX operation, one needs to clear the FX_SEL bit of Mode Control
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* Register.
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*/
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void reset_phy(void)
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{
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unsigned short mode_control;
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miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
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miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
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mode_control & 0xfffe);
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return;
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}
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#ifndef CONFIG_SYS_RAMBOOT
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/*
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* Helper function to initialize SDRAM controller.
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*/
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static void sdram_start(int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
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hi_addr_bit;
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
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hi_addr_bit;
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
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hi_addr_bit;
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/* auto refresh, second time */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
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hi_addr_bit;
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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}
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#endif /* !CONFIG_SYS_RAMBOOT */
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/*
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* Initalize SDRAM - configure SDRAM controller, detect memory size.
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*/
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phys_size_t initdram(int board_type)
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{
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ulong dramsize = 0;
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* According to AN3221 (MPC5200B SDRAM Initialization and
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* Configuration), the SDelay register must be written a value of
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* 0x00000004 as the first step of the SDRAM contorller configuration.
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*/
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*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
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/* configure SDRAM start/end for detection */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20))
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dramsize = 0;
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
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__builtin_ffs(dramsize >> 20) - 1;
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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}
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/* let SDRAM CS1 start right after CS0 and disable it */
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*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
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#else /* !CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13)
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dramsize = (1 << (dramsize - 0x13)) << 20;
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else
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dramsize = 0;
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#endif /* CONFIG_SYS_RAMBOOT */
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/* return total ram size */
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return dramsize;
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}
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int checkboard(void)
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{
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uchar rev = *(vu_char *)CPLD_REV_REGISTER;
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printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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return 0;
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#if defined(CONFIG_STATUS_LED)
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void __led_init(led_id_t regaddr, int state)
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{
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*((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
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if (state == STATUS_LED_ON)
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*((vu_long *) regaddr) |= LED_ON;
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else
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*((vu_long *) regaddr) &= ~LED_ON;
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}
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void __led_set(led_id_t regaddr, int state)
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{
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if (state == STATUS_LED_ON)
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*((vu_long *) regaddr) |= LED_ON;
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else
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*((vu_long *) regaddr) &= ~LED_ON;
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}
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void __led_toggle(led_id_t regaddr)
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{
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*((vu_long *) regaddr) ^= LED_ON;
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}
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#endif /* CONFIG_STATUS_LED */
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