mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
423 lines
13 KiB
C
423 lines
13 KiB
C
/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* Wolfgang Denk <wd@denx.de>
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Socrates
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
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#define CONFIG_MPC8544 1
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#define CONFIG_SOCRATES 1
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#define CONFIG_PCI
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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/*
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* sysclk for MPC85xx
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*
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* Two valid values are:
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* 33000000
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* 66000000
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*
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* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
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* is likely the desired value here, so that is now the default.
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* The board, however, can run at 66MHz. In any event, this value
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* must match the settings of some switches. Details can be found
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* in the README.mpc85xxads.
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*/
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 66666666
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#endif
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00000000
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#define CFG_MEMTEST_END 0x10000000
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
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#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
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#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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/*
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* DDR Setup
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*/
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
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/* Hardcoded values, to use instead of SPD */
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#define CFG_DDR_CS0_BNDS 0x0000000f
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#define CFG_DDR_CS0_CONFIG 0x80010102
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#define CFG_DDR_TIMING_0 0x00260802
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#define CFG_DDR_TIMING_1 0x3935D322
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#define CFG_DDR_TIMING_2 0x14904CC8
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#define CFG_DDR_MODE 0x00480432
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#define CFG_DDR_INTERVAL 0x030C0100
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#define CFG_DDR_CONFIG_2 0x04400000
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#define CFG_DDR_CONFIG 0xC3008000
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#define CFG_DDR_CLK_CONTROL 0x03800000
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#define CFG_SDRAM_SIZE 256 /* in Megs */
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
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#define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
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/*
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* Flash on the Local Bus
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*/
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/*
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* Flash on the LocalBus
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*/
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#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
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#define CFG_FLASH0 0xFE000000
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#define CFG_FLASH1 0xFC000000
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
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#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
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#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
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#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */
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#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */
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#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */
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#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
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#define CFG_FLASH_CFI /* flash is CFI compat. */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
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#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
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#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
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#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
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#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
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#define CONFIG_L1_INIT_RAM
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
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#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/*
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* I2C
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/* I2C RTC */
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#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
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#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */
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/* I2C temp sensor */
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/* Socrates uses Maxim's DS75, which is compatible with LM75 */
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#define CONFIG_DTT_LM75 1
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#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
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#define CFG_DTT_MAX_TEMP 125
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#define CFG_DTT_LOW_TEMP -55
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#define CFG_DTT_HYSTERESIS 3
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#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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/*
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* General PCI
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* Memory space is mapped 1-1.
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*/
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#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
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/* PCI is clocked by the external source at 33 MHz */
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#define CONFIG_PCI_CLK_FREQ 33000000
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_IO_BASE 0xE2000000
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#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
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#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
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#if defined(CONFIG_PCI)
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "TSEC1"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC3_FLAGS TSEC_GIGABIT
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/* Options are: TSEC[0,1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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/*
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* Environment
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_TIMESTAMP /* Print image info with ts */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DTT
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#undef CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SNTP
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#define CONFIG_CMD_USB
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
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#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootfile=$hostname/uImage\0" \
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"netdev=eth0\0" \
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"consdev=ttyS0\0" \
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"hostname=socrates\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
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":$hostname:$netdev:off panic=1\0" \
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"addcons=setenv bootargs $bootargs " \
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"console=$consdev,$baudrate\0" \
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"flash_self=run ramargs addip addcons;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
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"flash_nfs=run nfsargs addip addcons;" \
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"bootm ${kernel_addr} - ${fdt_addr}\0" \
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"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
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"tftp ${fdt_addr_r} ${fdt_file}; " \
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"run nfsargs addip addcons;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"fdt_file=$hostname/socrates.dtb\0" \
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"fdt_addr_r=B00000\0" \
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"fdt_addr=FC1E0000\0" \
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"rootpath=/opt/eldk/ppc_85xxDP\0" \
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"kernel_addr=FC000000\0" \
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"kernel_addr_r=200000\0" \
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"ramdisk_addr=FC200000\0" \
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"ramdisk_addr_r=400000\0" \
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"load=tftp 100000 $hostname/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b 100000 fffc0000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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/* USB support */
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_PCI_OHCI 1
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#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
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#define CFG_OHCI_SWAP_REG_ACCESS 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_USB_STORAGE 1
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/* FPGA and NAND */
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#define CFG_FPGA_BASE 0xc0000000
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#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
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#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */
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#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70)
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_CMD_NAND
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#endif /* __CONFIG_H */
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