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the DRAM Controller in i.MX8MP will support a feature called "Inline ECC". This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and DDR3L). When this feature is enabled by software, the DRAM Controller reserves 12.5% of DRAM capacity for ECC information, and presents only the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to the rest of the SoC. The DRAM memory can be divided into 8 regions so that if a use case only requires ECC protection on a subset of memory, then only that subset of memory need support inline ECC. If this occurs, then there is no performance penalty accessing the non-ECC-protected memory (no need to access ECC for this portion of the memory map). This is all configured with the DRAM Controller. Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
40 lines
906 B
Plaintext
40 lines
906 B
Plaintext
menu "i.MX8M DDR controllers"
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depends on ARCH_IMX8M
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config IMX8M_DRAM
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bool "imx8m dram"
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config IMX8M_LPDDR4
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bool "imx8m lpddr4"
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select IMX8M_DRAM
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help
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Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
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config IMX8M_DDR4
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bool "imx8m ddr4"
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select IMX8M_DRAM
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help
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Select the i.MX8M DDR4 driver support on i.MX8M SOC.
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config IMX8M_DDR3L
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bool "imx8m ddr3l"
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select IMX8M_DRAM
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help
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Select the i.MX8M DDR3L driver support on i.MX8M SOC.
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config SAVED_DRAM_TIMING_BASE
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hex "Define the base address for saved dram timing"
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help
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after DRAM is trained, need to save the dram related timming
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info into memory for low power use. OCRAM_S is used for this
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purpose on i.MX8MM.
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default 0x180000
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config IMX8M_DRAM_INLINE_ECC
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bool "imx8mp inline ECC"
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depends on IMX8MP && IMX8M_LPDDR4
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help
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Select this config if you want to use inline ecc feature for
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imx8mp-evk board.
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endmenu
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