mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
299 lines
8.0 KiB
C
299 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <linux/bitfield.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/sizes.h>
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#include <linux/libfdt.h>
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#include <mmc.h>
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#include <sdhci.h>
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/* HRS - Host Register Set (specific to Cadence) */
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#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
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#define SDHCI_CDNS_HRS04_ACK BIT(26)
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#define SDHCI_CDNS_HRS04_RD BIT(25)
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#define SDHCI_CDNS_HRS04_WR BIT(24)
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#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
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#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
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#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
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#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
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#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
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#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
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#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
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#define SDHCI_CDNS_HRS06_MODE_SD 0x0
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#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
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#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
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/* SRS - Slot Register Set (SDHCI-compatible) */
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#define SDHCI_CDNS_SRS_BASE 0x200
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/* PHY */
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#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
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#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
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#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
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#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
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#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
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#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
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#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
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#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
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#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
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/*
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* The tuned val register is 6 bit-wide, but not the whole of the range is
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* available. The range 0-42 seems to be available (then 43 wraps around to 0)
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* but I am not quite sure if it is official. Use only 0 to 39 for safety.
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*/
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#define SDHCI_CDNS_MAX_TUNING_LOOP 40
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struct sdhci_cdns_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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void __iomem *hrs_addr;
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};
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struct sdhci_cdns_phy_cfg {
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const char *property;
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u8 addr;
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};
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static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
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{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
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{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
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{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
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{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
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{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
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{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
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{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
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{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
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{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
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{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
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{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
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};
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static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
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u8 addr, u8 data)
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{
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void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
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u32 tmp;
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int ret;
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tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
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FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
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writel(tmp, reg);
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tmp |= SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
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if (ret)
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return ret;
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tmp &= ~SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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return 0;
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}
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static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
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const void *fdt, int nodeoffset)
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{
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const fdt32_t *prop;
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int ret, i;
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for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
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prop = fdt_getprop(fdt, nodeoffset,
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sdhci_cdns_phy_cfgs[i].property, NULL);
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if (!prop)
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continue;
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ret = sdhci_cdns_write_phy_reg(plat,
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sdhci_cdns_phy_cfgs[i].addr,
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fdt32_to_cpu(*prop));
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if (ret)
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return ret;
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}
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return 0;
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}
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static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
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{
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struct mmc *mmc = host->mmc;
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struct sdhci_cdns_plat *plat = dev_get_platdata(mmc->dev);
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unsigned int clock = mmc->clock;
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u32 mode, tmp;
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/*
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* REVISIT:
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* The mode should be decided by MMC_TIMING_* like Linux, but
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* U-Boot does not support timing. Use the clock frequency instead.
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*/
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if (clock <= 26000000) {
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mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
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} else if (clock <= 52000000) {
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if (mmc->ddr_mode)
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mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
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else
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mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
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} else {
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if (mmc->ddr_mode)
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
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else
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
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}
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tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
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tmp &= ~SDHCI_CDNS_HRS06_MODE;
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tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
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writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
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}
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static const struct sdhci_ops sdhci_cdns_ops = {
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.set_control_reg = sdhci_cdns_set_control_reg,
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};
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static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
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unsigned int val)
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{
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void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
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u32 tmp;
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if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
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return -EINVAL;
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tmp = readl(reg);
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tmp &= ~SDHCI_CDNS_HRS06_TUNE;
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tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
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tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
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writel(tmp, reg);
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return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
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1);
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}
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static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
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unsigned int opcode)
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{
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struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
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struct mmc *mmc = &plat->mmc;
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int cur_streak = 0;
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int max_streak = 0;
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int end_of_streak = 0;
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int i;
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/*
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* This handler only implements the eMMC tuning that is specific to
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* this controller. The tuning for SD timing should be handled by the
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* SDHCI core.
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*/
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if (!IS_MMC(mmc))
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return -ENOTSUPP;
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if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
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return -EINVAL;
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for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
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if (sdhci_cdns_set_tune_val(plat, i) ||
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mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
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cur_streak = 0;
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} else { /* good */
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cur_streak++;
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if (cur_streak > max_streak) {
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max_streak = cur_streak;
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end_of_streak = i;
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}
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}
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}
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if (!max_streak) {
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dev_err(dev, "no tuning point found\n");
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return -EIO;
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}
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return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
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}
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static struct dm_mmc_ops sdhci_cdns_mmc_ops;
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static int sdhci_cdns_bind(struct udevice *dev)
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{
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struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
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return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static int sdhci_cdns_probe(struct udevice *dev)
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{
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DECLARE_GLOBAL_DATA_PTR;
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
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struct sdhci_host *host = dev_get_priv(dev);
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fdt_addr_t base;
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int ret;
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base = devfdt_get_addr(dev);
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if (base == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
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if (!plat->hrs_addr)
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return -ENOMEM;
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host->name = dev->name;
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host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
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host->ops = &sdhci_cdns_ops;
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host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
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sdhci_cdns_mmc_ops = sdhci_ops;
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#ifdef MMC_SUPPORTS_TUNING
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sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
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#endif
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ret = mmc_of_parse(dev, &plat->cfg);
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if (ret)
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return ret;
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ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
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if (ret)
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return ret;
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ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
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if (ret)
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return ret;
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upriv->mmc = &plat->mmc;
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host->mmc = &plat->mmc;
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host->mmc->priv = host;
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return sdhci_probe(dev);
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}
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static const struct udevice_id sdhci_cdns_match[] = {
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{ .compatible = "socionext,uniphier-sd4hc" },
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{ .compatible = "cdns,sd4hc" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(sdhci_cdns) = {
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.name = "sdhci-cdns",
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.id = UCLASS_MMC,
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.of_match = sdhci_cdns_match,
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.bind = sdhci_cdns_bind,
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.probe = sdhci_cdns_probe,
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.priv_auto_alloc_size = sizeof(struct sdhci_host),
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.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
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.ops = &sdhci_cdns_mmc_ops,
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};
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