mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
b41411954d
U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008,2009
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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static struct pci_controller coreboot_hose;
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static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *table)
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{
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u8 secondary;
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hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
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hose->last_busno = max(hose->last_busno, (int)secondary);
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pci_hose_scan_bus(hose, secondary);
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}
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static struct pci_config_table pci_coreboot_config_table[] = {
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/* vendor, device, class, bus, dev, func */
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
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{}
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};
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void pci_init_board(void)
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{
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coreboot_hose.config_table = pci_coreboot_config_table;
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coreboot_hose.first_busno = 0;
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coreboot_hose.last_busno = 0;
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pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
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PCI_REGION_MEM);
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coreboot_hose.region_count = 1;
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pci_setup_type1(&coreboot_hose);
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pci_register_hose(&coreboot_hose);
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pci_hose_scan(&coreboot_hose);
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}
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