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https://github.com/brain-hackers/u-boot-brain
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37bfd9cb50
Add basic support for the Hitachi Power Grids kmcent2 board, based on the NXP QorIQ T1040 SoC. Signed-off-by: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> Signed-off-by: Rainer Boschung <rainer.boschung@hitachi-powergrids.com> Signed-off-by: Niel Fourie <lusus@denx.de> Cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> [Fixed blank line at EOF errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
105 lines
3.7 KiB
C
105 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Keymile AG
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* Rainer Boschung <rainer.boschung@keymile.com>
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <asm/mmu.h>
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#include <asm/u-boot.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 0, BOOKE_PAGESZ_4K, 1),
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 1, BOOKE_PAGESZ_16M, 1),
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/* *I*G* - Flash, localbus */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
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0, 2, BOOKE_PAGESZ_128M, 1),
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/* *I*G* - PCI1 */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 3, BOOKE_PAGESZ_1G, 1),
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/* *I*G* - PCI1 I/O */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 4, BOOKE_PAGESZ_256K, 1),
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/* Bman/Qman */
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SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 5, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
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CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 6, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, 0,
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0, 7, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
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CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 8, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 9, BOOKE_PAGESZ_4M, 1),
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/* *I*G - NAND */
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 10, BOOKE_PAGESZ_64K, 1),
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/* QRIO */
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SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
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MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 11, BOOKE_PAGESZ_64K, 1),
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/* MRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
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MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 12, BOOKE_PAGESZ_128M, 1),
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/* BFTIC */
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SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
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MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 13, BOOKE_PAGESZ_128M, 1),
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/*
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* entry 14 and 15 has been used hard coded, they will be disabled
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* in cpu_init_f, so do not use them here!!.
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*/
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/* PAXE */
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SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS,
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MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, 16, BOOKE_PAGESZ_128M, 1)
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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