mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
4ffc39050a
Added the CONFIG_M5271 to the list of Coldfire V2 processor. This was causing the bus clock (not CPU clock) to be declared twice as fast as it actually is. This causes UARTS to operate at half the specified baudrate. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
/*
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* (C) Copyright 2003
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* Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* get_clocks() fills in gd->cpu_clock and gd->bus_clk
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*/
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int get_clocks (void)
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{
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
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volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
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unsigned long pllcr;
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#ifndef CONFIG_SYS_PLL_BYPASS
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#ifdef CONFIG_M5249
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/* Setup the PLL to run at the specified speed */
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#ifdef CONFIG_SYS_FAST_CLK
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pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
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#else
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pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
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#endif
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#endif /* CONFIG_M5249 */
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#ifdef CONFIG_M5253
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pllcr = CONFIG_SYS_PLLCR;
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#endif /* CONFIG_M5253 */
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cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
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pllcr ^= 0x00000001; /* Set pll bypass to 1 */
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
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udelay(0x20); /* Wait for a lock ... */
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#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
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#endif /* CONFIG_M5249 || CONFIG_M5253 */
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#if defined(CONFIG_M5275)
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volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
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/* Setup PLL */
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pll->syncr = 0x01080000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK))
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;
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pll->syncr = 0x01000000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK))
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;
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#endif
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gd->cpu_clk = CONFIG_SYS_CLK;
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
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defined(CONFIG_M5271) || defined(CONFIG_M5275)
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gd->bus_clk = gd->cpu_clk / 2;
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#else
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gd->bus_clk = gd->cpu_clk;
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#endif
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#ifdef CONFIG_FSL_I2C
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gd->i2c1_clk = gd->bus_clk;
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#ifdef CONFIG_SYS_I2C2_OFFSET
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gd->i2c2_clk = gd->bus_clk;
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#endif
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#endif
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return (0);
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}
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