Alexey Brodkin 379b3280b3 arc: cache - accommodate different L1 cache line lengths ... ARC core could be configured with different L1 and L2 (AKA SLC) cache line lengths. At least these values are possible and were really used: 32, 64 or 128 bytes. Current implementation requires cache line to be selected upon U-Boot configuration and then it will only work on matching hardware. Indeed this is quite efficient because cache line length gets hardcoded during code compilation. But OTOH it makes binary less portable. With this commit we allow U-Boot to determine real L1 cache line length early in runtime and use this value later on. This extends portability of U-Boot binary a lot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		2016-02-20 11:19:53 +03:00
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cpu	arc: make sure _start is in the beginning of .text section	2015-04-10 18:45:34 +03:00
dts	axs103: add support of generic OHCI USB 1.1 controller	2015-12-21 23:29:04 +03:00
include/asm	arc: cache - accommodate different L1 cache line lengths	2016-02-20 11:19:53 +03:00
lib	arc: cache - accommodate different L1 cache line lengths	2016-02-20 11:19:53 +03:00
config.mk	arc: use more universal prefix for default CROSS_COMPILE	2015-05-13 13:44:25 +03:00
Kconfig	arc: cache - accommodate different L1 cache line lengths	2016-02-20 11:19:53 +03:00
Makefile	arc: introduce separate section for interrupt vector table	2015-01-15 22:38:42 +03:00