mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Sagar Shrikant Kadam](/assets/img/avatar_default.png)
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
14 lines
250 B
C
14 lines
250 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (c) 2020 SiFive, Inc.
|
|
*
|
|
* Author: Sagar Kadam <sagar.kadam@sifive.com>
|
|
*/
|
|
|
|
#ifndef __RESET_SIFIVE_H
|
|
#define __RESET_SIFIVE_H
|
|
|
|
int sifive_reset_bind(struct udevice *dev, ulong count);
|
|
|
|
#endif
|