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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
188 lines
4.8 KiB
C
188 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* Common functions for OMAP4 based boards
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*/
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#include <common.h>
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#include <palmas.h>
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#include <asm/armv7.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/sizes.h>
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#include <asm/emif.h>
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#include <asm/arch/gpio.h>
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#include <asm/omap_common.h>
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u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
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static const struct gpio_bank gpio_bank_44xx[6] = {
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{ (void *)OMAP44XX_GPIO1_BASE },
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{ (void *)OMAP44XX_GPIO2_BASE },
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{ (void *)OMAP44XX_GPIO3_BASE },
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{ (void *)OMAP44XX_GPIO4_BASE },
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{ (void *)OMAP44XX_GPIO5_BASE },
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{ (void *)OMAP44XX_GPIO6_BASE },
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
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#ifdef CONFIG_SPL_BUILD
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/*
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* Some tuning of IOs for optimal power and performance
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*/
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void do_io_settings(void)
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{
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u32 lpddr2io;
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u32 omap4_rev = omap_revision();
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if (omap4_rev == OMAP4430_ES1_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
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else if (omap4_rev == OMAP4430_ES2_0)
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lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
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else
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lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
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/* EMIF1 */
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writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
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writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
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/* No pull for GR10 as per hw team's recommendation */
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writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
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(*ctrl)->control_lpddr2io1_2);
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writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
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/* EMIF2 */
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writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
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writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
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/* No pull for GR10 as per hw team's recommendation */
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writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
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(*ctrl)->control_lpddr2io2_2);
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writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
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/*
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* Some of these settings (TRIM values) come from eFuse and are
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* in turn programmed in the eFuse at manufacturing time after
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* calibration of the device. Do the software over-ride only if
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* the device is not correctly trimmed
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*/
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if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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(*ctrl)->control_ldosram_iva_voltage_ctrl);
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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(*ctrl)->control_ldosram_mpu_voltage_ctrl);
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writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
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(*ctrl)->control_ldosram_core_voltage_ctrl);
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}
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/*
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* Over-ride the register
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* i. unconditionally for all 4430
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* ii. only if un-trimmed for 4460
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*/
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if (!readl((*ctrl)->control_efuse_1))
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writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
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if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
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writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
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}
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#endif /* CONFIG_SPL_BUILD */
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/* dummy fuction for omap4 */
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void config_data_eye_leveling_samples(u32 emif_base)
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{
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}
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void init_omap_revision(void)
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{
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/*
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* For some of the ES2/ES1 boards ID_CODE is not reliable:
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* Also, ES1 and ES2 have different ARM revisions
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* So use ARM revision for identification
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*/
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unsigned int arm_rev = cortex_rev();
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switch (arm_rev) {
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case MIDR_CORTEX_A9_R0P1:
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*omap_si_rev = OMAP4430_ES1_0;
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break;
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case MIDR_CORTEX_A9_R1P2:
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switch (readl(CONTROL_ID_CODE)) {
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case OMAP4_CONTROL_ID_CODE_ES2_0:
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*omap_si_rev = OMAP4430_ES2_0;
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break;
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case OMAP4_CONTROL_ID_CODE_ES2_1:
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*omap_si_rev = OMAP4430_ES2_1;
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break;
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case OMAP4_CONTROL_ID_CODE_ES2_2:
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*omap_si_rev = OMAP4430_ES2_2;
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break;
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default:
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*omap_si_rev = OMAP4430_ES2_0;
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break;
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}
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break;
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case MIDR_CORTEX_A9_R1P3:
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*omap_si_rev = OMAP4430_ES2_3;
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break;
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case MIDR_CORTEX_A9_R2P10:
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switch (readl(CONTROL_ID_CODE)) {
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case OMAP4470_CONTROL_ID_CODE_ES1_0:
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*omap_si_rev = OMAP4470_ES1_0;
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break;
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case OMAP4460_CONTROL_ID_CODE_ES1_1:
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*omap_si_rev = OMAP4460_ES1_1;
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break;
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case OMAP4460_CONTROL_ID_CODE_ES1_0:
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default:
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*omap_si_rev = OMAP4460_ES1_0;
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break;
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}
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break;
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default:
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*omap_si_rev = OMAP4430_SILICON_ID_INVALID;
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break;
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}
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}
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void omap_die_id(unsigned int *die_id)
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{
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die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
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die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
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die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
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die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
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}
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#ifndef CONFIG_SYS_L2CACHE_OFF
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void v7_outer_cache_enable(void)
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{
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omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
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}
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void v7_outer_cache_disable(void)
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{
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omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
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}
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#endif /* !CONFIG_SYS_L2CACHE_OFF */
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void vmmc_pbias_config(uint voltage)
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{
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u32 value = 0;
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value = readl((*ctrl)->control_pbiaslite);
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value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
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writel(value, (*ctrl)->control_pbiaslite);
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value = readl((*ctrl)->control_pbiaslite);
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value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
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writel(value, (*ctrl)->control_pbiaslite);
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}
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