Simon Glass 2b6051541b x86: ivybridge: Add early LPC init so that serial works ... The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>		2014-11-21 07:34:12 +01:00
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include	Makefile: Support include files for .dts files	2014-06-20 11:55:03 -06:00
.gitignore	dts: generate multiple device tree blobs	2014-02-19 11:10:05 -05:00
alex.dts	dts: move device tree sources to arch/$(ARCH)/dts/	2014-02-19 11:10:05 -05:00
chromebook_link.dts	x86: Add chromebook_link board	2014-11-21 07:34:11 +01:00
coreboot.dtsi	dm: x86: Convert coreboot serial to use driver model	2014-10-23 19:45:45 -06:00
link.dts	x86: ivybridge: Add early LPC init so that serial works	2014-11-21 07:34:12 +01:00
Makefile	x86: Add chromebook_link board	2014-11-21 07:34:11 +01:00
skeleton.dtsi	x86: fdt: Create basic .dtsi file for coreboot	2012-12-06 14:30:42 -08:00