mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 13:46:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
107 lines
3.5 KiB
C
107 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* UniPhier UMC (Universal Memory Controller) registers
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*
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* Copyright (C) 2011-2014 Panasonic Corporation
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*/
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#ifndef ARCH_UMC_REGS_H
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#define ARCH_UMC_REGS_H
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#include <linux/bitops.h>
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#define UMC_CPURST 0x00000700
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#define UMC_IDSRST 0x0000070C
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#define UMC_IXMRST 0x00000714
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#define UMC_HDMRST 0x00000718
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#define UMC_MDMRST 0x0000071C
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#define UMC_HDDRST 0x00000720
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#define UMC_MDDRST 0x00000724
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#define UMC_SIORST 0x00000728
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#define UMC_GIORST 0x0000072C
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#define UMC_HD2RST 0x00000734
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#define UMC_VIORST 0x0000073C
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#define UMC_FRCRST 0x00000748 /* LD4/sLD8 */
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#define UMC_DVCRST 0x00000748 /* Pro4 */
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#define UMC_RGLRST 0x00000750
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#define UMC_VPERST 0x00000758
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#define UMC_AIORST 0x00000764
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#define UMC_DMDRST 0x00000770
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#define UMC_HDMCHSEL 0x00000898
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#define UMC_MDMCHSEL 0x0000089C
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#define UMC_DVCCHSEL 0x000008C8
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#define UMC_DMDCHSEL 0x000008F0
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#define UMC_CLKEN_SSIF_FETCH 0x0000C060
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#define UMC_CLKEN_SSIF_COMQUE0 0x0000C064
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#define UMC_CLKEN_SSIF_COMWC0 0x0000C068
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#define UMC_CLKEN_SSIF_COMRC0 0x0000C06C
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#define UMC_CLKEN_SSIF_COMQUE1 0x0000C070
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#define UMC_CLKEN_SSIF_COMWC1 0x0000C074
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#define UMC_CLKEN_SSIF_COMRC1 0x0000C078
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#define UMC_CLKEN_SSIF_WC 0x0000C07C
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#define UMC_CLKEN_SSIF_RC 0x0000C080
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#define UMC_CLKEN_SSIF_DST 0x0000C084
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#define UMC_CMDCTLA 0x00000000
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#define UMC_CMDCTLB 0x00000004
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#define UMC_INITSET 0x00000014
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#define UMC_INITSET_INIT1EN BIT(1) /* init without power-on wait */
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#define UMC_INITSET_INIT0EN BIT(0) /* init with power-on wait */
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#define UMC_INITSTAT 0x00000018
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#define UMC_INITSTAT_INIT1ST BIT(1) /* init without power-on wait */
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#define UMC_INITSTAT_INIT0ST BIT(0) /* init with power-on wait */
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#define UMC_SPCCTLA 0x00000030
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#define UMC_SPCCTLB 0x00000034
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#define UMC_SPCSETA 0x00000038
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#define UMC_SPCSETB 0x0000003C
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#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */
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#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */
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#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */
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#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */
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#define UMC_SPCSETC 0x00000040
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#define UMC_SPCSETD 0x00000044
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#define UMC_SPCSTATA 0x00000050
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#define UMC_SPCSTATB 0x00000054
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#define UMC_SPCSTATC 0x00000058
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#define UMC_ACSSETA 0x00000060
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#define UMC_FLOWCTLA 0x00000400
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#define UMC_FLOWCTLB 0x00000404
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#define UMC_FLOWCTLC 0x00000408
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#define UMC_FLOWCTLG 0x00000508
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#define UMC_FLOWCTLOB0 0x00000520
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#define UMC_FLOWCTLOB1 0x00000524
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#define UMC_RDATACTL_D0 0x00000600
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#define UMC_RDATACTL_RADLTY_SHIFT 4
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#define UMC_RDATACTL_RADLTY_MASK (0xf << (UMC_RDATACTL_RADLTY_SHIFT))
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#define UMC_RDATACTL_RAD2LTY_SHIFT 8
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#define UMC_RDATACTL_RAD2LTY_MASK (0xf << (UMC_RDATACTL_RAD2LTY_SHIFT))
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#define UMC_WDATACTL_D0 0x00000604
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#define UMC_RDATACTL_D1 0x00000608
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#define UMC_WDATACTL_D1 0x0000060C
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#define UMC_DATASET 0x00000610
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#define UMC_RESPCTL 0x00000624
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#define UMC_DCCGCTL 0x00000720
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#define UMC_DICGCTLA 0x00000724
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#define UMC_DICGCTLB 0x00000728
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#define UMC_ERRMASKA 0x00000958
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#define UMC_ERRMASKB 0x0000095c
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#define UMC_BSICMAPSET 0x00000988
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#define UMC_DIOCTLA 0x00000C00
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#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */
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#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */
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#define UMC_DFICUPDCTLA 0x00000C20
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/* UM registers */
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#define UMC_MBUS0 0x00080004
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#define UMC_MBUS1 0x00081004
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#define UMC_MBUS2 0x00082004
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#define UMC_MBUS3 0x00083004
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/* UD registers */
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#define UMC_BITPERPIXELMODE_D0 0x010
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#define UMC_PAIR1DOFF_D0 0x054
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#endif
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