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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-10 23:03:29 +09:00
![Fabio Estevam](/assets/img/avatar_default.png)
On qong board some of the USBH2 pins are set via GPR register, so don need to setup the IOMUX for each pin individually. Other than that, these pins should not be configured as primary function because the primary function selects SSI functionality. Let GPR register do the work and remove the unneeded IOMUX setup. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
277 lines
7.7 KiB
C
277 lines
7.7 KiB
C
/*
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*
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* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <pmic.h>
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#include <fsl_pmic.h>
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#include <asm/gpio.h>
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#include "qong_fpga.h"
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_HW_WATCHDOG
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void hw_watchdog_reset(void)
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{
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mxc_hw_watchdog_reset();
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}
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void qong_fpga_reset(void)
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{
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gpio_set_value(QONG_FPGA_RST_PIN, 0);
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udelay(30);
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gpio_set_value(QONG_FPGA_RST_PIN, 1);
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udelay(300);
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_QONG_FPGA
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/* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
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static const struct mxc_weimcs cs1 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(1, &cs1);
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/* setup pins for FPGA */
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mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
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mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
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/* FPGA reset Pin */
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/* rstn = 0 */
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gpio_direction_output(QONG_FPGA_RST_PIN, 0);
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/* set interrupt pin as input */
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gpio_direction_input(QONG_FPGA_IRQ_PIN);
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/* FPGA JTAG Interface */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
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gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
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gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
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gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
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gpio_direction_input(QONG_FPGA_TDO_PIN);
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#endif
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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/* setup pins for SPI (pmic) */
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mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
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mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
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mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
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mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
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mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
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/* Setup pins for USB2 Host */
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
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#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
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PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
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mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
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mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
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mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
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mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
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mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
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mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
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mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
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mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
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mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
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mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
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mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
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mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
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mx31_set_gpr(MUX_PGP_UH2, 1);
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return 0;
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}
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int board_init(void)
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{
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/* Chip selects */
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/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
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/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(0, &cs0);
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/* board id for linux */
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gd->bd->bi_arch_number = MACH_TYPE_QONG;
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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qong_fpga_init();
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return 0;
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}
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int board_late_init(void)
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{
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u32 val;
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struct pmic *p;
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pmic_init();
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p = get_pmic();
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/* Enable RTC battery */
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pmic_reg_read(p, REG_POWER_CTL0, &val);
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pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
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pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
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#ifdef CONFIG_HW_WATCHDOG
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mxc_hw_watchdog_enable();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: DAVE/DENX Qong\n");
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return 0;
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}
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int misc_init_r(void)
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{
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#ifdef CONFIG_QONG_FPGA
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u32 tmp;
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tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
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printf("FPGA: ");
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printf("version register = %u.%u.%u\n",
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(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
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#endif
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
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return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
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#else
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return 0;
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#endif
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}
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#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
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static void board_nand_setup(void)
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{
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/* CS3: NAND 8-bit */
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static const struct mxc_weimcs cs3 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(3, &cs3);
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__REG(IOMUXC_GPR) |= 1 << 13;
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
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/* Make sure to reset the fpga else you cannot access NAND */
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qong_fpga_reset();
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/* Enable NAND flash */
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gpio_set_value(15, 1);
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gpio_set_value(14, 1);
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gpio_direction_output(15, 0);
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gpio_direction_input(16);
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gpio_direction_input(14);
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}
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int qong_nand_rdy(void *chip)
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{
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udelay(1);
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return gpio_get_value(16);
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}
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void qong_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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if (chip >= 0)
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gpio_set_value(15, 0);
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else
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gpio_set_value(15, 1);
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}
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void qong_nand_plat_init(void *chip)
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{
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struct nand_chip *nand = (struct nand_chip *)chip;
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nand->chip_delay = 20;
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nand->select_chip = qong_nand_select_chip;
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nand->options &= ~NAND_BUSWIDTH_16;
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board_nand_setup();
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}
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#endif
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