mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-11 20:53:44 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010-2015
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA_H_
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#define _TEGRA_H_
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#define NV_PA_ARM_PERIPHBASE 0x50040000
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#define NV_PA_PG_UP_BASE 0x60000000
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#define NV_PA_TMRUS_BASE 0x60005010
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#define NV_PA_CLK_RST_BASE 0x60006000
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#define NV_PA_FLOW_BASE 0x60007000
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#define NV_PA_GPIO_BASE 0x6000D000
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#define NV_PA_EVP_BASE 0x6000F000
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#define NV_PA_APB_MISC_BASE 0x70000000
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#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
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#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
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#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
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#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
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#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
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#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
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#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
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#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
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#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
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#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
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#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
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#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
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#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
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#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
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#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
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#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
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#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
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#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
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#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
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defined(CONFIG_TEGRA114)
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#define NV_PA_CSITE_BASE 0x70040000
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#else
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#define NV_PA_CSITE_BASE 0x70800000
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#endif
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#define TEGRA_USB_ADDR_MASK 0xFFFFC000
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#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
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#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
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#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000)
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#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096)
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#define PG_UP_TAG_AVP 0xAAAAAAAA
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#ifndef __ASSEMBLY__
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struct timerus {
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unsigned int cntr_1us;
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};
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/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
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#define NV_WB_RUN_ADDRESS 0x40020000
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#define NVBOOTTYPE_RECOVERY 2 /* BR entered RCM */
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#define NVBOOTINFOTABLE_BOOTTYPE 0xC /* Boot type in BIT in IRAM */
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#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
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#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
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/* These are the available SKUs (product types) for Tegra */
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enum {
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SKU_ID_T20_7 = 0x7,
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SKU_ID_T20 = 0x8,
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SKU_ID_T25SE = 0x14,
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SKU_ID_AP25 = 0x17,
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SKU_ID_T25 = 0x18,
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SKU_ID_AP25E = 0x1b,
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SKU_ID_T25E = 0x1c,
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SKU_ID_T33 = 0x80,
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SKU_ID_T30 = 0x81, /* Cardhu value */
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SKU_ID_TM30MQS_P_A3 = 0xb1,
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SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
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SKU_ID_T114_1 = 0x01,
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SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
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SKU_ID_T210_ENG = 0x00, /* unfused value TBD */
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};
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/*
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* These are used to distinguish SOC types for setting up clocks. Mostly
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* we can tell the clocking required by looking at the SOC sku_id, but
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* for T30 it is a user option as to whether to run PLLP in fast or slow
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* mode, so we have two options there.
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*/
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enum {
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TEGRA_SOC_T20,
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TEGRA_SOC_T25,
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TEGRA_SOC_T30,
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TEGRA_SOC_T114,
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TEGRA_SOC_T124,
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TEGRA_SOC_T210,
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TEGRA_SOC_CNT,
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TEGRA_SOC_UNKNOWN = -1,
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};
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/* Tegra system controller (SYSCON) devices */
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enum {
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TEGRA_SYSCON_PMC,
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};
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#else /* __ASSEMBLY__ */
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#define PRM_RSTCTRL NV_PA_PMC_BASE
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#endif
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#endif /* TEGRA_H */
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