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https://github.com/brain-hackers/u-boot-brain
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![Ruchika Gupta](/assets/img/avatar_default.png)
Freescale's SEC block has built-in Blob Protocol which provides a method for protecting user-defined data across system power cycles. SEC block protects data in a data structure called a Blob, which provides both confidentiality and integrity protection. Encapsulating data as a blob Each time that the Blob Protocol is used to protect data, a different randomly generated key is used to encrypt the data. This random key is itself encrypted using a key which is derived from SoC's non volatile secret key and a 16 bit Key identifier. The resulting encrypted key along with encrypted data is called a blob. The non volatile secure key is available for use only during secure boot. During decapsulation, the reverse process is performed to get back the original data. Commands added -------------- blob enc - encapsulating data as a cryptgraphic blob blob dec - decapsulating cryptgraphic blob to get the data Commands Syntax --------------- blob enc src dst len km Encapsulate and create blob of data $len bytes long at address $src and store the result at address $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. blob dec src dst len km Decapsulate the blob of data at address $src and store result of $len byte at addr $dst. $km is the 16 byte key modifier is also required for generation/use as key for cryptographic operation. Key modifier should be 16 byte long. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
182 lines
4.9 KiB
C
182 lines
4.9 KiB
C
/*
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* Common internal memory map for some Freescale SoCs
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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*/
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#ifndef __FSL_SEC_H
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#define __FSL_SEC_H
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#include <common.h>
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#include <asm/io.h>
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#ifdef CONFIG_SYS_FSL_SEC_LE
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#define sec_in32(a) in_le32(a)
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#define sec_out32(a, v) out_le32(a, v)
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#define sec_in16(a) in_le16(a)
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#define sec_clrbits32 clrbits_le32
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#define sec_setbits32 setbits_le32
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#elif defined(CONFIG_SYS_FSL_SEC_BE)
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#define sec_in32(a) in_be32(a)
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#define sec_out32(a, v) out_be32(a, v)
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#define sec_in16(a) in_be16(a)
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#define sec_clrbits32 clrbits_be32
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#define sec_setbits32 setbits_be32
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#else
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#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
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#endif
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/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
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#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
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/* RNG4 TRNG test registers */
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struct rng4tst {
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#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
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u32 rtmctl; /* misc. control register */
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u32 rtscmisc; /* statistical check misc. register */
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u32 rtpkrrng; /* poker range register */
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#define RTSDCTL_ENT_DLY_MIN 1200
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#define RTSDCTL_ENT_DLY_MAX 12800
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union {
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u32 rtpkrmax; /* PRGM=1: poker max. limit register */
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u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
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};
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#define RTSDCTL_ENT_DLY_SHIFT 16
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#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
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u32 rtsdctl; /* seed control register */
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union {
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u32 rtsblim; /* PRGM=1: sparse bit limit register */
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u32 rttotsam; /* PRGM=0: total samples register */
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};
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u32 rtfreqmin; /* frequency count min. limit register */
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union {
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u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
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u32 rtfreqcnt; /* PRGM=0: freq. count register */
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};
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u32 rsvd1[40];
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#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
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u32 rdsta; /*RNG DRNG Status Register*/
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u32 rsvd2[15];
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};
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typedef struct ccsr_sec {
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u32 res0;
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u32 mcfgr; /* Master CFG Register */
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u8 res1[0x4];
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u32 scfgr;
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struct {
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u32 ms; /* Job Ring LIODN Register, MS */
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u32 ls; /* Job Ring LIODN Register, LS */
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} jrliodnr[4];
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u8 res2[0x2c];
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u32 jrstartr; /* Job Ring Start Register */
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struct {
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u32 ms; /* RTIC LIODN Register, MS */
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u32 ls; /* RTIC LIODN Register, LS */
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} rticliodnr[4];
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u8 res3[0x1c];
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u32 decorr; /* DECO Request Register */
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struct {
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u32 ms; /* DECO LIODN Register, MS */
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u32 ls; /* DECO LIODN Register, LS */
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} decoliodnr[8];
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u8 res4[0x40];
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u32 dar; /* DECO Avail Register */
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u32 drr; /* DECO Reset Register */
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u8 res5[0x4d8];
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struct rng4tst rng; /* RNG Registers */
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u8 res11[0x8a0];
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u32 crnr_ms; /* CHA Revision Number Register, MS */
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u32 crnr_ls; /* CHA Revision Number Register, LS */
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u32 ctpr_ms; /* Compile Time Parameters Register, MS */
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u32 ctpr_ls; /* Compile Time Parameters Register, LS */
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u8 res6[0x10];
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u32 far_ms; /* Fault Address Register, MS */
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u32 far_ls; /* Fault Address Register, LS */
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u32 falr; /* Fault Address LIODN Register */
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u32 fadr; /* Fault Address Detail Register */
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u8 res7[0x4];
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u32 csta; /* CAAM Status Register */
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u8 res8[0x8];
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u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
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u32 ccbvid; /* CHA Cluster Block Version ID Register */
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u32 chavid_ms; /* CHA Version ID Register, MS */
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u32 chavid_ls; /* CHA Version ID Register, LS */
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u32 chanum_ms; /* CHA Number Register, MS */
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u32 chanum_ls; /* CHA Number Register, LS */
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u32 secvid_ms; /* SEC Version ID Register, MS */
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u32 secvid_ls; /* SEC Version ID Register, LS */
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u8 res9[0x6020];
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u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
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u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
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u8 res10[0x8fd8];
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} ccsr_sec_t;
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#define SEC_CTPR_MS_AXI_LIODN 0x08000000
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#define SEC_CTPR_MS_QI 0x02000000
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#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
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#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
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#define SEC_RVID_MA 0x0f000000
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#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
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#define SEC_CHANUM_MS_JRNUM_SHIFT 28
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#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
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#define SEC_CHANUM_MS_DECONUM_SHIFT 24
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#define SEC_SECVID_MS_IPID_MASK 0xffff0000
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#define SEC_SECVID_MS_IPID_SHIFT 16
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#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
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#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
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#define SEC_CCBVID_ERA_MASK 0xff000000
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#define SEC_CCBVID_ERA_SHIFT 24
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#define SEC_SCFGR_RDBENABLE 0x00000400
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#define SEC_SCFGR_VIRT_EN 0x00008000
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#define SEC_CHAVID_LS_RNG_SHIFT 16
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#define SEC_CHAVID_RNG_LS_MASK 0x000f0000
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#define CONFIG_JRSTARTR_JR0 0x00000001
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struct jr_regs {
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#ifdef CONFIG_SYS_FSL_SEC_LE
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u32 irba_l;
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u32 irba_h;
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#else
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u32 irba_h;
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u32 irba_l;
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#endif
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u32 rsvd1;
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u32 irs;
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u32 rsvd2;
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u32 irsa;
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u32 rsvd3;
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u32 irja;
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#ifdef CONFIG_SYS_FSL_SEC_LE
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u32 orba_l;
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u32 orba_h;
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#else
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u32 orba_h;
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u32 orba_l;
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#endif
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u32 rsvd4;
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u32 ors;
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u32 rsvd5;
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u32 orjr;
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u32 rsvd6;
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u32 orsf;
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u32 rsvd7;
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u32 jrsta;
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u32 rsvd8;
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u32 jrint;
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u32 jrcfg0;
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u32 jrcfg1;
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u32 rsvd9;
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u32 irri;
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u32 rsvd10;
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u32 orwi;
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u32 rsvd11;
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u32 jrcr;
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};
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int sec_init(void);
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#endif
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#endif /* __FSL_SEC_H */
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