mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
77 lines
2.5 KiB
ArmAsm
77 lines
2.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/macro.h>
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.globl lowlevel_init
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lowlevel_init:
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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write32 IPU_CONF, IPU_CONF_DI_EN
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write32 CCM_CCMR, CCM_CCMR_SETUP
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wait_timer 0x40000
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write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
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write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
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/* Set up clock to 532MHz */
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write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
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write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
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write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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/* Set up MX31 DDR pins */
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write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
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write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
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write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
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write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
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write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
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write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
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write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
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write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
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write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
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write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
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write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
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write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
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write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
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write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
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write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
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write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
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write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
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write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
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write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
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write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
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write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
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write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
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write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
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write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
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write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
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write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
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write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
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/* Set up MX31 DDR Memory Controller */
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write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
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write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
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/* Perform DDR init sequence */
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write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
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write32 CSD0_BASE | 0x0f00, 0x12344321
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write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
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write32 CSD0_BASE, 0x12344321
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write32 CSD0_BASE, 0x12344321
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write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
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write8 CSD0_BASE | 0x00000033, 0xda
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write8 CSD0_BASE | 0x01000000, 0xff
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write32 WEIM_ESDCTL0, ESDCTL_RW
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write32 CSD0_BASE, 0xDEADBEEF
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write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
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mov pc, lr
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