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https://github.com/brain-hackers/u-boot-brain
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d32e86bde8
ARMV7_LPAE is required in order to enable the MMU in HYP mode. And we really want to enable the MMU in HYP mode such that we can enable the the caches. Otherwise U-Boot code (such as the EFI implementation) that runs in HYP mode will run at a snils pace. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
62 lines
1.6 KiB
Plaintext
62 lines
1.6 KiB
Plaintext
if CPU_V7A
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config CPU_V7_HAS_NONSEC
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bool
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config CPU_V7_HAS_VIRT
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bool
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config ARCH_SUPPORT_PSCI
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bool
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config ARMV7_NONSEC
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bool "Enable support for booting in non-secure mode" if EXPERT
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depends on CPU_V7_HAS_NONSEC
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default y
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---help---
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Say Y here to enable support for booting in non-secure / SVC mode.
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config ARMV7_BOOT_SEC_DEFAULT
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bool "Boot in secure mode by default" if EXPERT
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depends on ARMV7_NONSEC
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default y if TEGRA
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---help---
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Say Y here to boot in secure mode by default even if non-secure mode
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is supported. This option is useful to boot kernels which do not
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suppport booting in non-secure mode. Only set this if you need it.
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This can be overridden at run-time by setting the bootm_boot_mode env.
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variable to "sec" or "nonsec".
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config ARMV7_VIRT
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bool "Enable support for hardware virtualization" if EXPERT
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depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
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default y
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---help---
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Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
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config ARMV7_PSCI
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bool "Enable PSCI support" if EXPERT
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depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
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default y
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help
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Say Y here to enable PSCI support.
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config ARMV7_PSCI_NR_CPUS
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int "Maximum supported CPUs for PSCI"
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depends on ARMV7_NONSEC
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default 4
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help
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The maximum number of CPUs supported in the PSCI firmware.
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It is no problem to set a larger value than the number of
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CPUs in the actual hardware implementation.
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config ARMV7_LPAE
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bool "Use LPAE page table format" if EXPERT
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depends on CPU_V7A
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default y if ARMV7_VIRT
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---help---
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Say Y here to use the long descriptor page table format. This is
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required if U-Boot runs in HYP mode.
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endif
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