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![Simon Glass](/assets/img/avatar_default.png)
Unfortunately a recent change adjusted the order of the checks here such
that 400MHz now shows up as fast-plus speed (1Mbps). Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: d96440d1e3
("i2c: designware_i2c: Add support for fast-plus speed")
783 lines
19 KiB
C
783 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <pci.h>
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#include <reset.h>
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#include <asm/io.h>
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#include "designware_i2c.h"
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
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static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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{
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u32 ena = enable ? IC_ENABLE_0B : 0;
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writel(ena, &i2c_base->ic_enable);
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return 0;
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}
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#else
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static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
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{
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u32 ena = enable ? IC_ENABLE_0B : 0;
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int timeout = 100;
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do {
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writel(ena, &i2c_base->ic_enable);
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if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
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return 0;
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/*
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* Wait 10 times the signaling period of the highest I2C
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* transfer supported by the driver (for 400KHz this is
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* 25us) as described in the DesignWare I2C databook.
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*/
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udelay(25);
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} while (timeout--);
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printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
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return -ETIMEDOUT;
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}
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#endif
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/* High and low times in different speed modes (in ns) */
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enum {
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/* SDA Hold Time */
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DEFAULT_SDA_HOLD_TIME = 300,
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};
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/**
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* calc_counts() - Convert a period to a number of IC clk cycles
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*
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* @ic_clk: Input clock in Hz
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* @period_ns: Period to represent, in ns
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* @return calculated count
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*/
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static uint calc_counts(uint ic_clk, uint period_ns)
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{
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return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
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}
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/**
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* struct i2c_mode_info - Information about an I2C speed mode
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*
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* Each speed mode has its own characteristics. This struct holds these to aid
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* calculations in dw_i2c_calc_timing().
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*
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* @speed: Speed in Hz
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* @min_scl_lowtime_ns: Minimum value for SCL low period in ns
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* @min_scl_hightime_ns: Minimum value for SCL high period in ns
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* @def_rise_time_ns: Default rise time in ns
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* @def_fall_time_ns: Default fall time in ns
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*/
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struct i2c_mode_info {
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int speed;
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int min_scl_hightime_ns;
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int min_scl_lowtime_ns;
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int def_rise_time_ns;
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int def_fall_time_ns;
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};
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static const struct i2c_mode_info info_for_mode[] = {
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[IC_SPEED_MODE_STANDARD] = {
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I2C_SPEED_STANDARD_RATE,
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MIN_SS_SCL_HIGHTIME,
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MIN_SS_SCL_LOWTIME,
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1000,
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300,
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},
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[IC_SPEED_MODE_FAST] = {
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I2C_SPEED_FAST_RATE,
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MIN_FS_SCL_HIGHTIME,
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MIN_FS_SCL_LOWTIME,
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300,
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300,
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},
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[IC_SPEED_MODE_FAST_PLUS] = {
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I2C_SPEED_FAST_PLUS_RATE,
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MIN_FP_SCL_HIGHTIME,
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MIN_FP_SCL_LOWTIME,
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260,
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500,
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},
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[IC_SPEED_MODE_HIGH] = {
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I2C_SPEED_HIGH_RATE,
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MIN_HS_SCL_HIGHTIME,
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MIN_HS_SCL_LOWTIME,
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120,
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120,
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},
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};
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/**
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* dw_i2c_calc_timing() - Calculate the timings to use for a bus
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*
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* @priv: Bus private information (NULL if not using driver model)
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* @mode: Speed mode to use
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* @ic_clk: IC clock speed in Hz
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* @spk_cnt: Spike-suppression count
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* @config: Returns value to use
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* @return 0 if OK, -EINVAL if the calculation failed due to invalid data
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*/
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static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
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int ic_clk, int spk_cnt,
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struct dw_i2c_speed_config *config)
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{
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int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
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int hcnt, lcnt, period_cnt, diff, tot;
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int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
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const struct i2c_mode_info *info;
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/*
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* Find the period, rise, fall, min tlow, and min thigh in terms of
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* counts of the IC clock
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*/
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info = &info_for_mode[mode];
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period_cnt = ic_clk / info->speed;
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scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
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priv->scl_rise_time_ns : info->def_rise_time_ns;
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scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
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priv->scl_fall_time_ns : info->def_fall_time_ns;
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rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
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fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
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min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
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min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
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debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
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period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
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spk_cnt);
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/*
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* Back-solve for hcnt and lcnt according to the following equations:
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* SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
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* SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
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*/
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hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
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lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
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if (hcnt < 0 || lcnt < 0) {
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debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
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return -EINVAL;
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}
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/*
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* Now add things back up to ensure the period is hit. If it is off,
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* split the difference and bias to lcnt for remainder
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*/
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tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
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if (tot < period_cnt) {
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diff = (period_cnt - tot) / 2;
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hcnt += diff;
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lcnt += diff;
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tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
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lcnt += period_cnt - tot;
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}
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config->scl_lcnt = lcnt;
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config->scl_hcnt = hcnt;
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/* Use internal default unless other value is specified */
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sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
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priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
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config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
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debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
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config->sda_hold);
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return 0;
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}
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static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
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struct dw_i2c_speed_config *config)
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{
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const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
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struct i2c_regs *regs = priv->regs;
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enum i2c_speed_mode i2c_spd;
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int spk_cnt;
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int ret;
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if (priv)
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scl_sda_cfg = priv->scl_sda_cfg;
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/* Allow high speed if there is no config, or the config allows it */
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if (speed >= I2C_SPEED_HIGH_RATE &&
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(!scl_sda_cfg || scl_sda_cfg->has_high_speed))
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i2c_spd = IC_SPEED_MODE_HIGH;
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else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
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i2c_spd = IC_SPEED_MODE_FAST_PLUS;
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else if (speed >= I2C_SPEED_FAST_RATE)
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i2c_spd = IC_SPEED_MODE_FAST;
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else
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i2c_spd = IC_SPEED_MODE_STANDARD;
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/* Get the proper spike-suppression count based on target speed */
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if (!priv || !priv->has_spk_cnt)
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spk_cnt = 0;
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else if (i2c_spd >= IC_SPEED_MODE_HIGH)
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spk_cnt = readl(®s->hs_spklen);
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else
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spk_cnt = readl(®s->fs_spklen);
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if (scl_sda_cfg) {
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config->sda_hold = scl_sda_cfg->sda_hold;
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if (i2c_spd == IC_SPEED_MODE_STANDARD) {
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config->scl_hcnt = scl_sda_cfg->ss_hcnt;
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config->scl_lcnt = scl_sda_cfg->ss_lcnt;
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} else {
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config->scl_hcnt = scl_sda_cfg->fs_hcnt;
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config->scl_lcnt = scl_sda_cfg->fs_lcnt;
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}
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} else {
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ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
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config);
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if (ret)
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return log_msg_ret("gen_confg", ret);
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}
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config->speed_mode = i2c_spd;
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return 0;
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}
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/*
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* _dw_i2c_set_bus_speed - Set the i2c speed
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* @speed: required i2c speed
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*
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* Set the i2c speed.
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*/
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static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
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unsigned int speed, unsigned int bus_clk)
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{
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struct dw_i2c_speed_config config;
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unsigned int cntl;
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unsigned int ena;
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int ret;
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ret = calc_bus_speed(priv, speed, bus_clk, &config);
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if (ret)
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return ret;
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/* Get enable setting for restore later */
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ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
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/* to set speed cltr must be disabled */
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dw_i2c_enable(i2c_base, false);
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cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
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switch (config.speed_mode) {
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case IC_SPEED_MODE_HIGH:
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cntl |= IC_CON_SPD_SS;
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writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
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writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
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break;
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case IC_SPEED_MODE_STANDARD:
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cntl |= IC_CON_SPD_SS;
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writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
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writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
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break;
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case IC_SPEED_MODE_FAST_PLUS:
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case IC_SPEED_MODE_FAST:
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default:
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cntl |= IC_CON_SPD_FS;
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writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
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writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
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break;
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}
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writel(cntl, &i2c_base->ic_con);
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/* Configure SDA Hold Time if required */
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if (config.sda_hold)
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writel(config.sda_hold, &i2c_base->ic_sda_hold);
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/* Restore back i2c now speed set */
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if (ena == IC_ENABLE_0B)
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dw_i2c_enable(i2c_base, true);
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return 0;
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}
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/*
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* i2c_setaddress - Sets the target slave address
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* @i2c_addr: target i2c address
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*
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* Sets the target slave address.
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*/
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static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
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{
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/* Disable i2c */
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dw_i2c_enable(i2c_base, false);
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writel(i2c_addr, &i2c_base->ic_tar);
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/* Enable i2c */
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dw_i2c_enable(i2c_base, true);
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}
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/*
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* i2c_flush_rxfifo - Flushes the i2c RX FIFO
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*
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* Flushes the i2c RX FIFO
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*/
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static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
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{
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while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
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readl(&i2c_base->ic_cmd_data);
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}
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/*
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* i2c_wait_for_bb - Waits for bus busy
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*
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* Waits for bus busy
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*/
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static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
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{
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unsigned long start_time_bb = get_timer(0);
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while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
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!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
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/* Evaluate timeout */
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if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
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return 1;
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}
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return 0;
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}
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static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
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int alen)
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{
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if (i2c_wait_for_bb(i2c_base))
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return 1;
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i2c_setaddress(i2c_base, chip);
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while (alen) {
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alen--;
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/* high byte address going out first */
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writel((addr >> (alen * 8)) & 0xff,
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&i2c_base->ic_cmd_data);
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}
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return 0;
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}
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static int i2c_xfer_finish(struct i2c_regs *i2c_base)
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{
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ulong start_stop_det = get_timer(0);
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while (1) {
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if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
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readl(&i2c_base->ic_clr_stop_det);
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break;
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} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
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break;
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}
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}
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if (i2c_wait_for_bb(i2c_base)) {
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printf("Timed out waiting for bus\n");
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return 1;
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}
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i2c_flush_rxfifo(i2c_base);
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return 0;
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}
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/*
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* i2c_read - Read from i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Read from i2c memory.
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*/
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static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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unsigned long start_time_rx;
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unsigned int active = 0;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(i2c_base, dev, addr, alen))
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return 1;
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start_time_rx = get_timer(0);
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while (len) {
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if (!active) {
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/*
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* Avoid writing to ic_cmd_data multiple times
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* in case this loop spins too quickly and the
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* ic_status RFNE bit isn't set after the first
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* write. Subsequent writes to ic_cmd_data can
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* trigger spurious i2c transfer.
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*/
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if (len == 1)
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writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
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else
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writel(IC_CMD, &i2c_base->ic_cmd_data);
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active = 1;
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}
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if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
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*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
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len--;
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start_time_rx = get_timer(0);
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active = 0;
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} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
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return 1;
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}
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}
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return i2c_xfer_finish(i2c_base);
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}
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/*
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* i2c_write - Write to i2c memory
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* @chip: target i2c address
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* @addr: address to read from
|
|
* @alen:
|
|
* @buffer: buffer for read data
|
|
* @len: no of bytes to be read
|
|
*
|
|
* Write to i2c memory.
|
|
*/
|
|
static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
|
|
int alen, u8 *buffer, int len)
|
|
{
|
|
int nb = len;
|
|
unsigned long start_time_tx;
|
|
|
|
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
/*
|
|
* EEPROM chips that implement "address overflow" are ones
|
|
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
* address and the extra bits end up in the "chip address"
|
|
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
|
* four 256 byte chips.
|
|
*
|
|
* Note that we consider the length of the address field to
|
|
* still be one byte because the extra address bits are
|
|
* hidden in the chip address.
|
|
*/
|
|
dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
|
|
|
|
debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
|
|
addr);
|
|
#endif
|
|
|
|
if (i2c_xfer_init(i2c_base, dev, addr, alen))
|
|
return 1;
|
|
|
|
start_time_tx = get_timer(0);
|
|
while (len) {
|
|
if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
|
|
if (--len == 0) {
|
|
writel(*buffer | IC_STOP,
|
|
&i2c_base->ic_cmd_data);
|
|
} else {
|
|
writel(*buffer, &i2c_base->ic_cmd_data);
|
|
}
|
|
buffer++;
|
|
start_time_tx = get_timer(0);
|
|
|
|
} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
|
|
printf("Timed out. i2c write Failed\n");
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return i2c_xfer_finish(i2c_base);
|
|
}
|
|
|
|
/*
|
|
* __dw_i2c_init - Init function
|
|
* @speed: required i2c speed
|
|
* @slaveaddr: slave address for the device
|
|
*
|
|
* Initialization function.
|
|
*/
|
|
static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
|
|
{
|
|
int ret;
|
|
|
|
/* Disable i2c */
|
|
ret = dw_i2c_enable(i2c_base, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
|
|
&i2c_base->ic_con);
|
|
writel(IC_RX_TL, &i2c_base->ic_rx_tl);
|
|
writel(IC_TX_TL, &i2c_base->ic_tx_tl);
|
|
writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
|
|
#ifndef CONFIG_DM_I2C
|
|
_dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
|
|
writel(slaveaddr, &i2c_base->ic_sar);
|
|
#endif
|
|
|
|
/* Enable i2c */
|
|
ret = dw_i2c_enable(i2c_base, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifndef CONFIG_DM_I2C
|
|
/*
|
|
* The legacy I2C functions. These need to get removed once
|
|
* all users of this driver are converted to DM.
|
|
*/
|
|
static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
|
|
{
|
|
switch (adap->hwadapnr) {
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 4
|
|
case 3:
|
|
return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
|
|
#endif
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 3
|
|
case 2:
|
|
return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
|
|
#endif
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 2
|
|
case 1:
|
|
return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
|
|
#endif
|
|
case 0:
|
|
return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
|
|
default:
|
|
printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
|
|
unsigned int speed)
|
|
{
|
|
adap->speed = speed;
|
|
return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
|
|
}
|
|
|
|
static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
|
{
|
|
__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
|
|
}
|
|
|
|
static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
|
|
int alen, u8 *buffer, int len)
|
|
{
|
|
return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
|
|
}
|
|
|
|
static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
|
|
int alen, u8 *buffer, int len)
|
|
{
|
|
return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
|
|
}
|
|
|
|
/* dw_i2c_probe - Probe the i2c chip */
|
|
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
|
|
{
|
|
struct i2c_regs *i2c_base = i2c_get_base(adap);
|
|
u32 tmp;
|
|
int ret;
|
|
|
|
/*
|
|
* Try to read the first location of the chip.
|
|
*/
|
|
ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
|
|
if (ret)
|
|
dw_i2c_init(adap, adap->speed, adap->slaveaddr);
|
|
|
|
return ret;
|
|
}
|
|
|
|
U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
|
dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
|
|
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 2
|
|
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
|
dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
|
|
#endif
|
|
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 3
|
|
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
|
dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
|
|
#endif
|
|
|
|
#if CONFIG_SYS_I2C_BUS_MAX >= 4
|
|
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
|
|
dw_i2c_write, dw_i2c_set_bus_speed,
|
|
CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
|
|
#endif
|
|
|
|
#else /* CONFIG_DM_I2C */
|
|
/* The DM I2C functions */
|
|
|
|
static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
|
|
int nmsgs)
|
|
{
|
|
struct dw_i2c *i2c = dev_get_priv(bus);
|
|
int ret;
|
|
|
|
debug("i2c_xfer: %d messages\n", nmsgs);
|
|
for (; nmsgs > 0; nmsgs--, msg++) {
|
|
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
|
|
if (msg->flags & I2C_M_RD) {
|
|
ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
|
|
msg->buf, msg->len);
|
|
} else {
|
|
ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
|
|
msg->buf, msg->len);
|
|
}
|
|
if (ret) {
|
|
debug("i2c_write: error sending\n");
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
|
|
{
|
|
struct dw_i2c *i2c = dev_get_priv(bus);
|
|
ulong rate;
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
rate = clk_get_rate(&i2c->clk);
|
|
if (IS_ERR_VALUE(rate))
|
|
return -EINVAL;
|
|
#else
|
|
rate = IC_CLK;
|
|
#endif
|
|
return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
|
|
}
|
|
|
|
static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
|
|
uint chip_flags)
|
|
{
|
|
struct dw_i2c *i2c = dev_get_priv(bus);
|
|
struct i2c_regs *i2c_base = i2c->regs;
|
|
u32 tmp;
|
|
int ret;
|
|
|
|
/* Try to read the first location of the chip */
|
|
ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
|
|
if (ret)
|
|
__dw_i2c_init(i2c_base, 0, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int designware_i2c_ofdata_to_platdata(struct udevice *bus)
|
|
{
|
|
struct dw_i2c *priv = dev_get_priv(bus);
|
|
int ret;
|
|
|
|
if (!priv->regs)
|
|
priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
|
|
dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
|
|
dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
|
|
dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
|
|
|
|
ret = reset_get_bulk(bus, &priv->resets);
|
|
if (ret)
|
|
dev_warn(bus, "Can't get reset: %d\n", ret);
|
|
else
|
|
reset_deassert_bulk(&priv->resets);
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
ret = clk_get_by_index(bus, 0, &priv->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_enable(&priv->clk);
|
|
if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
|
|
clk_free(&priv->clk);
|
|
dev_err(bus, "failed to enable clock\n");
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int designware_i2c_probe(struct udevice *bus)
|
|
{
|
|
struct dw_i2c *priv = dev_get_priv(bus);
|
|
|
|
return __dw_i2c_init(priv->regs, 0, 0);
|
|
}
|
|
|
|
int designware_i2c_remove(struct udevice *dev)
|
|
{
|
|
struct dw_i2c *priv = dev_get_priv(dev);
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
clk_disable(&priv->clk);
|
|
clk_free(&priv->clk);
|
|
#endif
|
|
|
|
return reset_release_bulk(&priv->resets);
|
|
}
|
|
|
|
const struct dm_i2c_ops designware_i2c_ops = {
|
|
.xfer = designware_i2c_xfer,
|
|
.probe_chip = designware_i2c_probe_chip,
|
|
.set_bus_speed = designware_i2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct udevice_id designware_i2c_ids[] = {
|
|
{ .compatible = "snps,designware-i2c" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(i2c_designware) = {
|
|
.name = "i2c_designware",
|
|
.id = UCLASS_I2C,
|
|
.of_match = designware_i2c_ids,
|
|
.ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
|
|
.probe = designware_i2c_probe,
|
|
.priv_auto_alloc_size = sizeof(struct dw_i2c),
|
|
.remove = designware_i2c_remove,
|
|
.flags = DM_FLAG_OS_PREPARE,
|
|
.ops = &designware_i2c_ops,
|
|
};
|
|
|
|
#endif /* CONFIG_DM_I2C */
|