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https://github.com/brain-hackers/u-boot-brain
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c97cd1ba48
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone. CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't seem right to overload it for meaning SPL as well as nand_spl does. Even if it's somewhat appropriate for the main u-boot, the SPL itself isn't (necessarily) ramboot, and we don't have separate configs for SPL and main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/global_data.h>
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#include <asm/fsl_ifc.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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void cpu_init_f(void)
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{
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#ifdef CONFIG_SYS_INIT_L2_ADDR
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ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
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/* set MBECCDIS=1, SBECCDIS=1 */
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out_be32(&l2cache->l2errdis,
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(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
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/* set L2E=1 & L2SRAM=001 */
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out_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
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#endif
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}
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#ifndef CONFIG_SYS_FSL_TBCLK_DIV
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#define CONFIG_SYS_FSL_TBCLK_DIV 8
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#endif
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void udelay(unsigned long usec)
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{
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u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
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u32 ticks = ticks_per_usec * usec;
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u32 s = mfspr(SPRN_TBRL);
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while ((mfspr(SPRN_TBRL) - s) < ticks);
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}
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