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![Simon Glass](/assets/img/avatar_default.png)
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
288 lines
6.6 KiB
C
288 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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/*
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* m8xx.c
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*
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* CPU specific code
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*
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* written or collected and sometimes rewritten by
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* Magnus Damm <damm@bitsmart.com>
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*
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* minor modifications by
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* Wolfgang Denk <wd@denx.de>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <net.h>
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#include <time.h>
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#include <vsprintf.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc8xx.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/cpm_8xx.h>
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#include <asm/global_data.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/* L1 i-cache */
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int checkicache(void)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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u32 cacheon = rd_ic_cst() & IDC_ENABLED;
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/* probe in flash memoryarea */
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u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
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u32 m;
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u32 lines = -1;
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wr_ic_cst(IDC_UNALL);
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wr_ic_cst(IDC_INVALL);
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wr_ic_cst(IDC_DISABLE);
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__asm__ volatile ("isync");
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while (!((m = rd_ic_cst()) & IDC_CERR2)) {
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wr_ic_adr(k);
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wr_ic_cst(IDC_LDLCK);
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__asm__ volatile ("isync");
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lines++;
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k += 0x10; /* the number of bytes in a cacheline */
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}
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wr_ic_cst(IDC_UNALL);
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wr_ic_cst(IDC_INVALL);
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if (cacheon)
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wr_ic_cst(IDC_ENABLE);
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else
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wr_ic_cst(IDC_DISABLE);
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__asm__ volatile ("isync");
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return lines << 4;
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};
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/* ------------------------------------------------------------------------- */
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/* L1 d-cache */
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/* call with cache disabled */
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static int checkdcache(void)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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u32 cacheon = rd_dc_cst() & IDC_ENABLED;
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/* probe in flash memoryarea */
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u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
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u32 m;
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u32 lines = -1;
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wr_dc_cst(IDC_UNALL);
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wr_dc_cst(IDC_INVALL);
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wr_dc_cst(IDC_DISABLE);
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while (!((m = rd_dc_cst()) & IDC_CERR2)) {
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wr_dc_adr(k);
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wr_dc_cst(IDC_LDLCK);
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lines++;
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k += 0x10; /* the number of bytes in a cacheline */
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}
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wr_dc_cst(IDC_UNALL);
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wr_dc_cst(IDC_INVALL);
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if (cacheon)
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wr_dc_cst(IDC_ENABLE);
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else
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wr_dc_cst(IDC_DISABLE);
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return lines << 4;
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};
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static int check_CPU(long clock, uint pvr, uint immr)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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uint k;
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char buf[32];
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/* the highest 16 bits should be 0x0050 for a 860 */
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if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
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return -1;
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k = (immr << 16) |
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in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
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/*
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* Some boards use sockets so different CPUs can be used.
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* We have to check chip version in run time.
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*/
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switch (k) {
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/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
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case 0x08010004: /* Rev. A.0 */
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printf("MPC866xxxZPnnA");
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break;
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case 0x08000003: /* Rev. 0.3 */
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printf("MPC866xxxZPnn");
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break;
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case 0x09000000: /* 870/875/880/885 */
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puts("MPC885ZPnn");
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break;
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default:
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printf("unknown MPC86x (0x%08x)", k);
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break;
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}
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printf(" at %s MHz: ", strmhz(buf, clock));
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print_size(checkicache(), " I-Cache ");
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print_size(checkdcache(), " D-Cache");
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/* do we have a FEC (860T/P or 852/859/866/885)? */
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out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
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if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
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printf(" FEC present");
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putc('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int checkcpu(void)
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{
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ulong clock = gd->cpu_clk;
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uint immr = get_immr(); /* Return full IMMR contents */
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uint pvr = get_pvr();
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puts("CPU: ");
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return check_CPU(clock, pvr, immr);
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}
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/* ------------------------------------------------------------------------- */
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void upmconfig(uint upm, uint *table, uint size)
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{
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uint i;
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uint addr = 0;
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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memctl8xx_t __iomem *memctl = &immap->im_memctl;
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for (i = 0; i < size; i++) {
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out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
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out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
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addr++;
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}
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}
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/* ------------------------------------------------------------------------- */
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int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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ulong msr, addr;
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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/* Checkstop Reset enable */
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setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
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/* Interrupts and MMU off */
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__asm__ volatile ("mtspr 81, 0");
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__asm__ volatile ("mfmsr %0" : "=r" (msr));
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msr &= ~0x1030;
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__asm__ volatile ("mtmsr %0" : : "r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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*/
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#ifdef CONFIG_SYS_RESET_ADDRESS
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addr = CONFIG_SYS_RESET_ADDRESS;
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#else
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/*
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* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
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* CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
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* Better pick an address known to be invalid on your system and assign
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* it to CONFIG_SYS_RESET_ADDRESS.
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* "(ulong)-1" used to be a good choice for many systems...
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*/
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addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
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#endif
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((void (*)(void)) addr)();
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return 1;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*
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* See sections 14.2 and 14.6 of the User's Manual
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*/
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unsigned long get_tbclk(void)
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{
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immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
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ulong oscclk, factor, pll;
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if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
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return gd->cpu_clk / 16;
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pll = in_be32(&immap->im_clkrst.car_plprcr);
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#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
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/*
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* For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
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* factor is calculated as follows:
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*
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* MFN
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* MFI + -------
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* MFD + 1
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* factor = -----------------
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* (PDF + 1) * 2^S
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*
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*/
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factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
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(PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
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oscclk = gd->cpu_clk / factor;
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if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
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factor > 2)
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return oscclk / 4;
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return oscclk / 16;
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}
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(struct bd_info *bis)
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{
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#if defined(CONFIG_MPC8XX_FEC)
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fec_initialize(bis);
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#endif
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return 0;
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}
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