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![Horatiu Vultur](/assets/img/avatar_default.png)
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common to support new numbe of pins and remove any platform dependency from mscc-common. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi SoCs pinctrl driver
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*
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* Author: <alexandre.belloni@free-electrons.com>
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* License: Dual MIT/GPL
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#define MSCC_FUNC_PER_PIN 4
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enum mscc_regs_gpio {
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MSCC_GPIO_OUT_SET,
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MSCC_GPIO_OUT_CLR,
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MSCC_GPIO_OUT,
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MSCC_GPIO_IN,
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MSCC_GPIO_OE,
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MSCC_GPIO_INTR,
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MSCC_GPIO_INTR_ENA,
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MSCC_GPIO_INTR_IDENT,
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MSCC_GPIO_ALT0,
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MSCC_GPIO_ALT1,
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};
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struct mscc_pin_caps {
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unsigned int pin;
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unsigned char functions[MSCC_FUNC_PER_PIN];
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};
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struct mscc_pin_data {
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const char *name;
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struct mscc_pin_caps *drv_data;
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};
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#define MSCC_P(p, f0, f1, f2) \
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static struct mscc_pin_caps mscc_pin_##p = { \
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.pin = p, \
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.functions = { \
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FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
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}, \
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}
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struct mscc_pmx_func {
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const char **groups;
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unsigned int ngroups;
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};
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struct mscc_pinctrl {
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struct udevice *dev;
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struct pinctrl_dev *pctl;
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void __iomem *regs;
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struct mscc_pmx_func *func;
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int num_func;
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const struct mscc_pin_data *mscc_pins;
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int num_pins;
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char * const *function_names;
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const unsigned long *mscc_gpios;
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};
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int mscc_pinctrl_probe(struct udevice *dev, int num_func,
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const struct mscc_pin_data *mscc_pins, int num_pins,
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char * const *function_names,
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const unsigned long *mscc_gpios);
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const struct pinctrl_ops mscc_pinctrl_ops;
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const struct dm_gpio_ops mscc_gpio_ops;
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