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u-boot-brain/board/freescale/ls1012ardb
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Biwen Li 164941c2c4 net: pfe_eth: read PFE ESBC header flash with spi_flash_read API 
Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
  Net:   SF: Detected s25fs512s with page size 256 Bytes, erase size 256
  KiB, total 64 MiB
  "Synchronous Abort" handler, esr 0x96000210
  elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
  elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
  x0 : 00000000b79407e8 x1 : 0000000040640000
  x2 : 0000000000000050 x3 : 0000000000000000
  x4 : 000000000000000a x5 : 0000000000000050
  x6 : 0000000000000366 x7 : 00000000b7942308
  x8 : 00000000b76407c0 x9 : 0000000000000008
  x10: 0000000000000044 x11: 00000000b7634d1c
  x12: 000000000000004f x13: 0000000000000044
  x14: 00000000b7634d98 x15: 00000000b76407c0
  x16: 0000000000000000 x17: 0000000000000000
  x18: 00000000b7636dd8 x19: 0000000000000000
  x20: 00000000b79407d0 x21: 00000000b79407e8
  x22: 0000000040640000 x23: 00000000b7634e58
  x24: 0000000000000000 x25: 0000000003800000
  x26: 00000000b7bdd000 x27: 0000000000000000
  x28: 0000000000000000 x29: 00000000b7634d10

  Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
  Resetting CPU ...

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-12-10 13:56:39 +05:30
..
eth.c armv8: ls1012a: RGMII ports require internal delay 2020-07-27 14:16:28 +05:30
Kconfig net: pfe_eth: read PFE ESBC header flash with spi_flash_read API 2020-12-10 13:56:39 +05:30
ls1012ardb.c treewide: convert bd_t to struct bd_info by coccinelle 2020-07-17 09:30:13 -04:00
MAINTAINERS Add TFA boot flow for some Layerscape platforms 2018-12-10 17:19:59 -05:00
Makefile board: freescale: ls1012ardb: enable network support on ls1012ardb 2018-03-22 15:05:30 -05:00
README board: ls1012a: LS1012A-2G5RDB board support 2018-01-15 11:56:33 -08:00

README 

Overview
--------
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
SoC overview.

LS1012ARDB board Overview
-----------------------
 - SERDES Connections, 4 lanes supporting:
      - PCI Express - 3.0
      - SGMII, SGMII 2.5
      - SATA 3.0
 - DDR Controller
     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
 -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
 signals to
    - QSPI NOR flash memory (2 virtual banks)
    - the QSPI emulator.s
 - USB 3.0
    - one high-speed USB 2.0/3.0 port.
 - Two enhanced secure digital host controllers:
    - SDHC1 controller can be connected to onboard SDHC connector
    - SDHC2 controller: Three dual 1:4 mux/demux devices,
    74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
    SDIO WiFi, SPI, and Ardiuno shield
 - 2 I2C controllers
 - One SATA onboard connectors
 - UART
   - The LS1012A processor consists of two UART controllers,
   out of which only UART1 is used on RDB.
 - ARM JTAG support

Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2

QSPI flash map
--------------
Images		| Size	|QSPI Flash Address
------------------------------------------
RCW + PBI	| 1MB	| 0x4000_0000
U-boot 		| 1MB	| 0x4010_0000
U-boot Env 	| 1MB	| 0x4020_0000
PPA FIT image	| 2MB	| 0x4050_0000
Linux ITB	| ~53MB | 0x40A0_0000

LS1012A2G5RDB board Overview
-----------------------
 - SERDES Connections, 3 lanes supporting:
      - SGMII, SGMII 2.5
      - SATA 3.0
 - DDR Controller
     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
 -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
 signals to
    - QSPI NOR flash memory
 - USB 3.0
    - one high-speed USB 2.0/3.0 port.
 - SDIO WiFi, SPI
 - 2 I2C controllers
 - One SATA onboard connectors
 - UART
   - The LS1012A processor consists of two UART controllers,
   out of which only UART1 is used on 2G5RDB.
 - ARM JTAG support

Major Difference between LS1012ARDB and LS1012A-2G5RDB
------------------------------------------------------
1. LS1012A-2G5RDB has Type C USB connector unlike USB Type A/B of LS1012ARDB
2. LS1012A-2G5RDB has 2 2.5G AQR PHY unlike 2 1G Realtek RTL8211FS PHYs
   of LS1012ARDB
3. LS1012A-2G5RDB is not having Arduino header
4. LS1012A-2G5RDB doesn't have PCI slot

Booting Options
---------------
QSPI Flash

QSPI flash map
--------------
Images		| Size	|QSPI Flash Address
------------------------------------------
RCW + PBI	| 1MB	| 0x4000_0000
U-boot 		| 1MB	| 0x4010_0000
U-boot Env 	| 1MB	| 0x4030_0000
PPA FIT image	| 2MB	| 0x4040_0000
PFE firmware	| 20K	| 0x00a0_0000
Linux ITB	| ~53MB | 0x4100_0000