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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
196 lines
4.2 KiB
C
196 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <mach/ddr.h>
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#include <mach/mc.h>
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#define DDR_BW_TEST_PAT 0xaa5555aa
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static const u32 dram_size[] = {
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[DRAM_8MB] = SZ_8M,
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[DRAM_16MB] = SZ_16M,
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[DRAM_32MB] = SZ_32M,
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[DRAM_64MB] = SZ_64M,
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[DRAM_128MB] = SZ_128M,
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[DRAM_256MB] = SZ_256M,
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};
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static void dram_test_write(u32 addr, u32 val)
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{
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volatile ulong *target = (volatile ulong *)(KSEG1 + addr);
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sync();
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*target = val;
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sync();
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}
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static u32 dram_test_read(u32 addr)
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{
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volatile ulong *target = (volatile ulong *)(KSEG1 + addr);
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u32 val;
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sync();
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val = *target;
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sync();
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return val;
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}
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static int dram_addr_test_bit(u32 bit)
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{
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u32 val;
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dram_test_write(0, 0);
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dram_test_write(BIT(bit), DDR_BW_TEST_PAT);
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val = dram_test_read(0);
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if (val == DDR_BW_TEST_PAT)
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return 1;
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return 0;
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}
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static void mc_ddr_init(void __iomem *memc, const struct mc_ddr_cfg *cfg,
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u32 dq_dly, u32 dqs_dly, mc_reset_t mc_reset, u32 bw)
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{
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u32 val;
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mc_reset(1);
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__udelay(200);
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mc_reset(0);
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clrbits_32(memc + MEMCTL_SDRAM_CFG1_REG, RBC_MAPPING);
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writel(cfg->cfg2, memc + MEMCTL_DDR_CFG2_REG);
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writel(cfg->cfg3, memc + MEMCTL_DDR_CFG3_REG);
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writel(cfg->cfg4, memc + MEMCTL_DDR_CFG4_REG);
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writel(dq_dly, memc + MEMCTL_DDR_DQ_DLY_REG);
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writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG);
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writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG);
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val = cfg->cfg1;
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if (bw) {
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val &= ~IND_SDRAM_WIDTH_M;
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val |= (bw << IND_SDRAM_WIDTH_S) & IND_SDRAM_WIDTH_M;
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}
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writel(val, memc + MEMCTL_DDR_CFG1_REG);
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clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M,
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1 << SR_TAR_CNT_S);
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setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
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}
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void ddr1_init(struct mc_ddr_init_param *param)
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{
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enum mc_dram_size sz;
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u32 bw = 0;
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/* First initialization, determine bus width */
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mc_ddr_init(param->memc, ¶m->cfgs[DRAM_8MB], param->dq_dly,
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param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT);
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/* Test bus width */
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dram_test_write(0, DDR_BW_TEST_PAT);
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if (dram_test_read(0) == DDR_BW_TEST_PAT)
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bw = IND_SDRAM_WIDTH_16BIT;
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else
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bw = IND_SDRAM_WIDTH_8BIT;
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/* Second initialization, determine DDR capacity */
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mc_ddr_init(param->memc, ¶m->cfgs[DRAM_128MB], param->dq_dly,
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param->dqs_dly, param->mc_reset, bw);
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if (dram_addr_test_bit(9)) {
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sz = DRAM_8MB;
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} else {
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if (dram_addr_test_bit(10)) {
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if (dram_addr_test_bit(23))
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sz = DRAM_16MB;
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else
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sz = DRAM_32MB;
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} else {
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if (dram_addr_test_bit(24))
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sz = DRAM_64MB;
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else
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sz = DRAM_128MB;
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}
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}
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/* Final initialization, with DDR calibration */
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mc_ddr_init(param->memc, ¶m->cfgs[sz], param->dq_dly,
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param->dqs_dly, param->mc_reset, bw);
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/* Return actual DDR configuration */
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param->memsize = dram_size[sz];
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param->bus_width = bw;
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}
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void ddr2_init(struct mc_ddr_init_param *param)
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{
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enum mc_dram_size sz;
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u32 bw = 0;
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/* First initialization, determine bus width */
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mc_ddr_init(param->memc, ¶m->cfgs[DRAM_32MB], param->dq_dly,
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param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT);
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/* Test bus width */
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dram_test_write(0, DDR_BW_TEST_PAT);
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if (dram_test_read(0) == DDR_BW_TEST_PAT)
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bw = IND_SDRAM_WIDTH_16BIT;
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else
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bw = IND_SDRAM_WIDTH_8BIT;
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/* Second initialization, determine DDR capacity */
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mc_ddr_init(param->memc, ¶m->cfgs[DRAM_256MB], param->dq_dly,
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param->dqs_dly, param->mc_reset, bw);
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if (bw == IND_SDRAM_WIDTH_16BIT) {
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if (dram_addr_test_bit(10)) {
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sz = DRAM_32MB;
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} else {
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if (dram_addr_test_bit(24)) {
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if (dram_addr_test_bit(27))
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sz = DRAM_64MB;
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else
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sz = DRAM_128MB;
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} else {
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sz = DRAM_256MB;
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}
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}
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} else {
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if (dram_addr_test_bit(23)) {
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sz = DRAM_32MB;
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} else {
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if (dram_addr_test_bit(24)) {
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if (dram_addr_test_bit(27))
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sz = DRAM_64MB;
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else
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sz = DRAM_128MB;
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} else {
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sz = DRAM_256MB;
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}
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}
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}
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/* Final initialization, with DDR calibration */
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mc_ddr_init(param->memc, ¶m->cfgs[sz], param->dq_dly,
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param->dqs_dly, param->mc_reset, bw);
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/* Return actual DDR configuration */
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param->memsize = dram_size[sz];
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param->bus_width = bw;
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}
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