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![Stefan Roese](/assets/img/avatar_default.png)
The current implementations have some issues detecting the correct values: dqs_find_max() will return "last passing fieldval + 1" instead of "last passing fieldval". Also it will return "maxval + 1" in the case that all fieldvals are tested valid (without error). dqs_find_min() will not test the "lowest" value because of using ">" instead of ">=". This patch now rewrites these functions to fix those issues. Also, this patch uses the same approach of a for loop in both functions making it easier to read and maintain. Since the variables are integers now, we can use min()/max(), which handles the wrap around case for fieldval=0: return (0 - 1). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
206 lines
5.2 KiB
C
206 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <mach/mc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define COARSE_MIN_START 6
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#define FINE_MIN_START 15
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#define COARSE_MAX_START 7
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#define FINE_MAX_START 0
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#define NUM_OF_CACHELINE 128
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#define TEST_PAT_SIZE (NUM_OF_CACHELINE * CONFIG_SYS_CACHELINE_SIZE)
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#define INIT_DQS_VAL ((7 << DQS1_DELAY_COARSE_TUNING_S) | \
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(4 << DQS1_DELAY_FINE_TUNING_S) | \
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(7 << DQS0_DELAY_COARSE_TUNING_S) | \
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(4 << DQS0_DELAY_FINE_TUNING_S))
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static inline void pref_op(int op, const volatile void *addr)
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{
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__asm__ __volatile__("pref %0, 0(%1)" : : "i" (op), "r" (addr));
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}
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static inline bool dqs_test_error(void __iomem *memc, u32 memsize, u32 dqsval,
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u32 bias)
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{
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u32 *nca, *ca;
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u32 off;
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int i;
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for (off = 0; off < memsize - TEST_PAT_SIZE; off += (memsize >> 6)) {
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nca = (u32 *)KSEG1ADDR(off);
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ca = (u32 *)KSEG0ADDR(off);
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writel(INIT_DQS_VAL, memc + MEMCTL_DDR_DQS_DLY_REG);
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wmb();
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for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++)
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ca[i] = 0x1f1f1f1f;
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for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++)
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nca[i] = (u32)nca + i + bias;
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writel(dqsval, memc + MEMCTL_DDR_DQS_DLY_REG);
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wmb();
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for (i = 0; i < TEST_PAT_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
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mips_cache(HIT_INVALIDATE_D, (u8 *)ca + i);
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wmb();
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for (i = 0; i < TEST_PAT_SIZE; i += CONFIG_SYS_CACHELINE_SIZE)
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pref_op(0, (u8 *)ca + i);
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for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++) {
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if (ca[i] != (u32)nca + i + bias)
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return true;
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}
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}
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return false;
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}
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static inline int dqs_find_max(void __iomem *memc, u32 memsize, int initval,
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int maxval, int shift, u32 regval)
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{
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int fieldval;
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u32 dqsval;
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for (fieldval = initval; fieldval <= maxval; fieldval++) {
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dqsval = regval | (fieldval << shift);
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if (dqs_test_error(memc, memsize, dqsval, 3))
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return max(fieldval - 1, initval);
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}
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return maxval;
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}
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static inline int dqs_find_min(void __iomem *memc, u32 memsize, int initval,
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int minval, int shift, u32 regval)
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{
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int fieldval;
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u32 dqsval;
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for (fieldval = initval; fieldval >= minval; fieldval--) {
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dqsval = regval | (fieldval << shift);
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if (dqs_test_error(memc, memsize, dqsval, 1))
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return min(fieldval + 1, initval);
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}
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return minval;
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}
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void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw)
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{
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u32 dqs_coarse_min, dqs_coarse_max, dqs_coarse_val;
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u32 dqs_fine_min, dqs_fine_max, dqs_fine_val;
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u32 dqs_coarse_min_limit, dqs_fine_min_limit;
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u32 dlls, dqs_dll, ddr_cfg2_reg;
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u32 dqs_dly_tmp, dqs_dly, test_dqs, shift;
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u32 rem, mask;
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int i;
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/* Disable Self-refresh */
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clrbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
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/* Save DDR_CFG2 and modify its DQS gating window */
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ddr_cfg2_reg = readl(memc + MEMCTL_DDR_CFG2_REG);
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mask = DQS0_GATING_WINDOW_M;
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if (bw == IND_SDRAM_WIDTH_16BIT)
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mask |= DQS1_GATING_WINDOW_M;
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clrbits_32(memc + MEMCTL_DDR_CFG2_REG, mask);
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/* Get minimum available DQS value */
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dlls = readl(memc + MEMCTL_DLL_DBG_REG);
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dlls = (dlls & MST_DLY_SEL_M) >> MST_DLY_SEL_S;
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dqs_dll = dlls >> 4;
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if (dqs_dll <= 8)
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dqs_coarse_min_limit = 8 - dqs_dll;
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else
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dqs_coarse_min_limit = 0;
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dqs_dll = dlls & 0xf;
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if (dqs_dll <= 8)
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dqs_fine_min_limit = 8 - dqs_dll;
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else
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dqs_fine_min_limit = 0;
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/* Initial DQS register value */
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dqs_dly = INIT_DQS_VAL;
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/* Calibrate DQS0 and/or DQS1 */
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for (i = 0; i < bw; i++) {
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shift = i * 8;
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dqs_dly &= ~(0xff << shift);
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/* Find maximum DQS coarse-grain */
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dqs_dly_tmp = dqs_dly | (0xf << shift);
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dqs_coarse_max = dqs_find_max(memc, memsize, COARSE_MAX_START,
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0xf, 4 + shift, dqs_dly_tmp);
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/* Find maximum DQS fine-grain */
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dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift));
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test_dqs = dqs_find_max(memc, memsize, FINE_MAX_START, 0xf,
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shift, dqs_dly_tmp);
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if (test_dqs == FINE_MAX_START) {
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dqs_coarse_max--;
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dqs_fine_max = 0xf;
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} else {
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dqs_fine_max = test_dqs - 1;
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}
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/* Find minimum DQS coarse-grain */
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dqs_dly_tmp = dqs_dly;
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dqs_coarse_min = dqs_find_min(memc, memsize, COARSE_MIN_START,
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dqs_coarse_min_limit, 4 + shift,
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dqs_dly_tmp);
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/* Find minimum DQS fine-grain */
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dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift));
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test_dqs = dqs_find_min(memc, memsize, FINE_MIN_START,
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dqs_fine_min_limit, shift, dqs_dly_tmp);
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if (test_dqs == FINE_MIN_START + 1) {
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dqs_coarse_min++;
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dqs_fine_min = 0;
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} else {
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dqs_fine_min = test_dqs;
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}
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/* Calculate central DQS coarse/fine value */
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dqs_coarse_val = (dqs_coarse_max + dqs_coarse_min) >> 1;
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rem = (dqs_coarse_max + dqs_coarse_min) % 2;
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dqs_fine_val = (rem * 4) + ((dqs_fine_max + dqs_fine_min) >> 1);
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if (dqs_fine_val >= 0x10) {
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dqs_coarse_val++;
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dqs_fine_val -= 8;
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}
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/* Save current DQS value */
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dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift;
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}
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/* Set final DQS value */
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writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG);
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/* Restore DDR_CFG2 */
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writel(ddr_cfg2_reg, memc + MEMCTL_DDR_CFG2_REG);
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/* Enable Self-refresh */
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setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN);
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}
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