588 lines
16 KiB
C
588 lines
16 KiB
C
/*
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* GE b1x5v2 - QMX6 SPL
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*
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* Copyright 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Copyright 2018-2020 GE Inc.
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* Copyright 2018-2020 Collabora Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <init.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <spl.h>
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#if defined(CONFIG_SPL_BUILD)
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#include <asm/arch/mx6-ddr.h>
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#define IMX6DQ_DRIVE_STRENGTH_40_OHM 0x30
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#define IMX6DQ_DRIVE_STRENGTH_48_OHM 0x28
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#define IMX6DQ_DRIVE_STRENGTH IMX6DQ_DRIVE_STRENGTH_40_OHM
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#define QMX6_DDR_PKE_DISABLED 0x00000000
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#define QMX6_DDR_ODT_60_OHM (2 << 16)
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#define QMX6_DDR_TYPE_DDR3 0x000c0000
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#define QMX6_DRAM_SDCKE_PULLUP_100K 0x00003000
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#define QMX6_DRAM_SDBA2_PULLUP_NONE 0x00000000
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#define SPI_PAD_CTRL (PAD_CTL_HYS | \
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PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define SPI1_CS0 IMX_GPIO_NR(3, 19)
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#define POWEROFF IMX_GPIO_NR(4, 25)
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static iomux_v3_cfg_t const poweroff_pads[] = {
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IOMUX_PADS(PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const uart2_pads[] = {
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IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const uart3_pads[] = {
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IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const ecspi1_pads[] = {
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IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
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.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_cas = IMX6DQ_DRIVE_STRENGTH,
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.dram_ras = IMX6DQ_DRIVE_STRENGTH,
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.dram_reset = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
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.dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
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.dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
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.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
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};
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static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
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.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_cas = IMX6DQ_DRIVE_STRENGTH,
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.dram_ras = IMX6DQ_DRIVE_STRENGTH,
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.dram_reset = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdcke0 = QMX6_DRAM_SDCKE_PULLUP_100K,
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.dram_sdcke1 = QMX6_DRAM_SDCKE_PULLUP_100K,
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.dram_sdba2 = QMX6_DRAM_SDBA2_PULLUP_NONE,
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.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
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};
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static struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
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.grp_ddr_type = QMX6_DDR_TYPE_DDR3,
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.grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
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.grp_ddrpke = QMX6_DDR_PKE_DISABLED,
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.grp_addds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ddrmode = QMX6_DDR_ODT_60_OHM,
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.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
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};
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static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = QMX6_DDR_TYPE_DDR3,
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.grp_ddrmode_ctl = QMX6_DDR_ODT_60_OHM,
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.grp_ddrpke = QMX6_DDR_PKE_DISABLED,
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.grp_addds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
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.grp_ddrmode = QMX6_DDR_ODT_60_OHM,
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.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
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.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
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};
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const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
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.p0_mpwldectrl0 = 0x0016001A,
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.p0_mpwldectrl1 = 0x0023001C,
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.p1_mpwldectrl0 = 0x0028003A,
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.p1_mpwldectrl1 = 0x001F002C,
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.p0_mpdgctrl0 = 0x43440354,
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.p0_mpdgctrl1 = 0x033C033C,
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.p1_mpdgctrl0 = 0x43300368,
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.p1_mpdgctrl1 = 0x03500330,
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.p0_mprddlctl = 0x3228242E,
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.p1_mprddlctl = 0x2C2C2636,
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.p0_mpwrdlctl = 0x36323A38,
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.p1_mpwrdlctl = 0x42324440,
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};
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const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00080016,
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.p0_mpwldectrl1 = 0x001D0016,
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.p1_mpwldectrl0 = 0x0018002C,
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.p1_mpwldectrl1 = 0x000D001D,
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.p0_mpdgctrl0 = 0x43200334,
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.p0_mpdgctrl1 = 0x0320031C,
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.p1_mpdgctrl0 = 0x0344034C,
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.p1_mpdgctrl1 = 0x03380314,
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.p0_mprddlctl = 0x3E36383A,
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.p1_mprddlctl = 0x38363240,
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.p0_mpwrdlctl = 0x36364238,
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.p1_mpwrdlctl = 0x4230423E,
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};
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const struct mx6_mmdc_calibration mx6q_4g_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00180018,
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.p0_mpwldectrl1 = 0x00220018,
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.p1_mpwldectrl0 = 0x00330046,
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.p1_mpwldectrl1 = 0x002B003D,
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.p0_mpdgctrl0 = 0x4344034C,
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.p0_mpdgctrl1 = 0x033C033C,
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.p1_mpdgctrl0 = 0x03700374,
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.p1_mpdgctrl1 = 0x03600338,
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.p0_mprddlctl = 0x443E3E40,
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.p1_mprddlctl = 0x423E3E48,
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.p0_mpwrdlctl = 0x3C3C4442,
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.p1_mpwrdlctl = 0x46384C46,
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};
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static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00480049,
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.p0_mpwldectrl1 = 0x00410044,
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.p0_mpdgctrl0 = 0x42480248,
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.p0_mpdgctrl1 = 0x023C023C,
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.p0_mprddlctl = 0x40424644,
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.p0_mpwrdlctl = 0x34323034,
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};
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static const struct mx6_mmdc_calibration mx6s_2g_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00450048,
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.p0_mpwldectrl1 = 0x003B003F,
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.p0_mpdgctrl0 = 0x424C0248,
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.p0_mpdgctrl1 = 0x0234023C,
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.p0_mprddlctl = 0x40444848,
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.p0_mpwrdlctl = 0x38363232,
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};
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static const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
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.p0_mpwldectrl0 = 0x0043004B,
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.p0_mpwldectrl1 = 0x003A003E,
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.p1_mpwldectrl0 = 0x0047004F,
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.p1_mpwldectrl1 = 0x004E0061,
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.p0_mpdgctrl0 = 0x42500250,
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.p0_mpdgctrl1 = 0x0238023C,
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.p1_mpdgctrl0 = 0x42640264,
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.p1_mpdgctrl1 = 0x02500258,
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.p0_mprddlctl = 0x40424846,
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.p1_mprddlctl = 0x46484842,
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.p0_mpwrdlctl = 0x38382C30,
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.p1_mpwrdlctl = 0x34343430,
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};
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static const struct mx6_mmdc_calibration mx6dl_2g_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00450045,
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.p0_mpwldectrl1 = 0x00390043,
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.p1_mpwldectrl0 = 0x0049004D,
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.p1_mpwldectrl1 = 0x004E0061,
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.p0_mpdgctrl0 = 0x4240023C,
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.p0_mpdgctrl1 = 0x0228022C,
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.p1_mpdgctrl0 = 0x02400244,
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.p1_mpdgctrl1 = 0x02340238,
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.p0_mprddlctl = 0x42464648,
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.p1_mprddlctl = 0x4446463C,
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.p0_mpwrdlctl = 0x3C38323A,
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.p1_mpwrdlctl = 0x34323430,
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};
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static struct mx6_ddr3_cfg mem_ddr_2g = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1310,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static struct mx6_ddr3_cfg mem_ddr_4g = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1310,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static struct mx6_ddr3_cfg mem_ddr_8g = {
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.mem_speed = 1600,
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.density = 8,
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.width = 16,
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.banks = 8,
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.rowaddr = 16,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1310,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void spl_dram_init(u8 width, u32 memsize) {
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struct mx6_ddr_sysinfo sysinfo = {
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/* width of data bus: 0=16, 1=32, 2=64 */
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.dsize = width / 32,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 2,
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.walat = 0,
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.ralat = 5,
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.mif3_mode = 3,
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.bi_on = 1,
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.sde_to_rst = 0x0d,
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.rst_to_cke = 0x20,
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};
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if (is_cpu_type(MXC_CPU_MX6SOLO)) {
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sysinfo.walat = 1;
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mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
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switch(memsize) {
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case 512:
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mx6_dram_cfg(&sysinfo, &mx6s_2g_mmcd_calib, &mem_ddr_2g);
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break;
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default:
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mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
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break;
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}
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} else if (is_cpu_type(MXC_CPU_MX6DL)) {
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sysinfo.walat = 1;
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mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
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switch(memsize) {
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case 2048:
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mx6_dram_cfg(&sysinfo, &mx6dl_2g_mmcd_calib, &mem_ddr_4g);
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break;
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default:
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mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
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break;
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}
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} else if (is_cpu_type(MXC_CPU_MX6Q)) {
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mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
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switch(memsize) {
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case 4096:
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sysinfo.cs_density = 16;
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sysinfo.ncs = 2;
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mx6_dram_cfg(&sysinfo, &mx6q_4g_mmcd_calib, &mem_ddr_8g);
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break;
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case 2048:
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mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
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break;
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default:
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mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
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break;
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}
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}
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}
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/* Define a minimal structure so that the part number can be read via SPL */
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#define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
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struct mfgdata {
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unsigned char tsize;
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/* size of checksummed part in bytes */
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unsigned char ckcnt;
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/* checksum corrected byte */
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unsigned char cksum;
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/* decimal serial number, packed BCD */
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unsigned char serial[6];
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/* part number, right justified, ASCII */
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unsigned char pn[16];
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};
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static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
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{
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int remain = len;
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unsigned char *sptr = src;
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unsigned char *dptr = dst;
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while (remain) {
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if (*sptr) {
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*dptr = *sptr;
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dptr++;
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}
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sptr++;
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remain--;
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}
|
|
*dptr = 0x0;
|
|
}
|
|
|
|
/*
|
|
* Returns the total size of the memory [in MB] the board is equipped with
|
|
*
|
|
* This is determined via the partnumber which is stored in the
|
|
* congatec manufacturing area
|
|
*/
|
|
static int get_boardmem_size(struct spi_flash *spi)
|
|
{
|
|
int ret;
|
|
int i;
|
|
int arraysize;
|
|
char buf[sizeof(struct mfgdata)];
|
|
struct mfgdata *data = (struct mfgdata *)buf;
|
|
unsigned char outbuf[32];
|
|
char partnumbers_2g[4][7] = { "016104", "016105", "016304", "016305" };
|
|
char partnumbers_4g[2][7] = { "016308", "016318" };
|
|
char partnumbers_512m[2][7] = { "016203", "616300" };
|
|
|
|
ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
|
|
buf);
|
|
if (ret)
|
|
return 1024; /* default to 1GByte in case of error */
|
|
|
|
conv_ascii(outbuf, data->pn, sizeof(data->pn));
|
|
|
|
printf("Detected Congatec QMX6 SOM: %s\n", outbuf);
|
|
|
|
/* congatec PN 016104, 016105, 016304, 016305 have 2GiB of RAM */
|
|
arraysize = sizeof(partnumbers_2g) / sizeof(partnumbers_2g[0]);
|
|
for (i=0; i < arraysize; i++) {
|
|
if (!memcmp(outbuf,partnumbers_2g[i],6))
|
|
return 2048;
|
|
}
|
|
|
|
/* congatec PN 016308, 016318 have 4GiB of RAM */
|
|
arraysize = sizeof(partnumbers_4g) / sizeof(partnumbers_4g[0]);
|
|
for (i=0; i < arraysize; i++) {
|
|
if (!memcmp(outbuf,partnumbers_4g[i],6))
|
|
return 4096;
|
|
}
|
|
|
|
/* congatec PN 016203, 616300 has 512MiB of RAM */
|
|
arraysize = sizeof(partnumbers_512m) / sizeof(partnumbers_512m[0]);
|
|
for (i=0; i < arraysize; i++) {
|
|
if (!memcmp(outbuf,partnumbers_512m[i],6))
|
|
return 512;
|
|
}
|
|
|
|
/* default to 1GByte */
|
|
return 1024;
|
|
}
|
|
|
|
void reset_cpu(void)
|
|
{
|
|
}
|
|
|
|
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
|
{
|
|
if (bus == 0 && cs == 0)
|
|
return (SPI1_CS0);
|
|
else
|
|
return -1;
|
|
}
|
|
|
|
static void memory_init(void) {
|
|
struct spi_flash *spi;
|
|
u8 width;
|
|
u32 size;
|
|
|
|
SETUP_IOMUX_PADS(ecspi1_pads);
|
|
gpio_direction_output(SPI1_CS0, 0);
|
|
|
|
spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
|
|
CONFIG_ENV_SPI_CS,
|
|
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
|
|
if (!spi)
|
|
panic("Cannot identify board type: SPI-NOR flash module not detected\n");
|
|
|
|
/* lock manufacturer area */
|
|
spi_flash_protect(spi, CFG_MFG_ADDR_OFFSET, SZ_16K, true);
|
|
|
|
width = is_cpu_type(MXC_CPU_MX6SOLO) ? 32 : 64;
|
|
size = get_boardmem_size(spi);
|
|
printf("Detected Memory Size: %u\n", size);
|
|
|
|
spl_dram_init(width, size);
|
|
}
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
static const uint32_t ccgr0 =
|
|
MXC_CCM_CCGR0_AIPS_TZ1_MASK |
|
|
MXC_CCM_CCGR0_AIPS_TZ2_MASK |
|
|
MXC_CCM_CCGR0_APBHDMA_MASK |
|
|
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK |
|
|
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
|
|
MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
|
|
MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK;
|
|
|
|
static const uint32_t ccgr1 =
|
|
MXC_CCM_CCGR1_ECSPI1S_MASK |
|
|
MXC_CCM_CCGR1_ENET_MASK |
|
|
MXC_CCM_CCGR1_EPIT1S_MASK |
|
|
MXC_CCM_CCGR1_EPIT2S_MASK |
|
|
MXC_CCM_CCGR1_GPT_BUS_MASK;
|
|
|
|
static const uint32_t ccgr2 =
|
|
MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK |
|
|
MXC_CCM_CCGR2_IPMUX1_MASK |
|
|
MXC_CCM_CCGR2_IPMUX2_MASK |
|
|
MXC_CCM_CCGR2_IPMUX3_MASK |
|
|
MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK |
|
|
MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK |
|
|
MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK;
|
|
|
|
static const uint32_t ccgr3 =
|
|
MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK |
|
|
MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK |
|
|
MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK |
|
|
MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK |
|
|
MXC_CCM_CCGR3_OCRAM_MASK;
|
|
|
|
static const uint32_t ccgr4 =
|
|
MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK |
|
|
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK |
|
|
MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK |
|
|
MXC_CCM_CCGR4_PWM1_MASK |
|
|
MXC_CCM_CCGR4_PWM2_MASK |
|
|
MXC_CCM_CCGR4_PWM3_MASK |
|
|
MXC_CCM_CCGR4_PWM4_MASK;
|
|
|
|
static const uint32_t ccgr5 =
|
|
MXC_CCM_CCGR5_ROM_MASK |
|
|
MXC_CCM_CCGR5_SDMA_MASK |
|
|
MXC_CCM_CCGR5_UART_MASK |
|
|
MXC_CCM_CCGR5_UART_SERIAL_MASK;
|
|
|
|
static const uint32_t ccgr6 =
|
|
MXC_CCM_CCGR6_USBOH3_MASK |
|
|
MXC_CCM_CCGR6_USDHC1_MASK |
|
|
MXC_CCM_CCGR6_USDHC2_MASK |
|
|
MXC_CCM_CCGR6_SIM1_CLK_MASK |
|
|
MXC_CCM_CCGR6_SIM2_CLK_MASK;
|
|
|
|
writel(ccgr0, &ccm->CCGR0);
|
|
writel(ccgr1, &ccm->CCGR1);
|
|
writel(ccgr2, &ccm->CCGR2);
|
|
writel(ccgr3, &ccm->CCGR3);
|
|
writel(ccgr4, &ccm->CCGR4);
|
|
writel(ccgr5, &ccm->CCGR5);
|
|
writel(ccgr6, &ccm->CCGR6);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
/* setup clock gating */
|
|
ccgr_init();
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
/* setup AXI */
|
|
gpr_init();
|
|
|
|
/*
|
|
* setup poweroff GPIO. This controls system power regulator. Once
|
|
* the power button is released this must be enabled to keep system
|
|
* running. Not enabling it (or disabling it later) will turn off
|
|
* the main system regulator and instantly poweroff the system. We
|
|
* do this very early, to reduce the time users have to press the
|
|
* power button.
|
|
*/
|
|
SETUP_IOMUX_PADS(poweroff_pads);
|
|
gpio_direction_output(POWEROFF, 1);
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* iomux */
|
|
if (CONFIG_MXC_UART_BASE == UART2_BASE)
|
|
SETUP_IOMUX_PADS(uart2_pads);
|
|
else if (CONFIG_MXC_UART_BASE == UART3_BASE)
|
|
SETUP_IOMUX_PADS(uart3_pads);
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* Needed for malloc() [used by SPI] to work in SPL prior to board_init_r() */
|
|
spl_init();
|
|
|
|
/* DDR initialization */
|
|
memory_init();
|
|
}
|
|
|
|
void spl_board_prepare_for_boot(void)
|
|
{
|
|
printf("Load normal U-Boot...\n");
|
|
}
|
|
#endif
|