138 lines
2.7 KiB
C
138 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020 - Cortina Access Inc.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/compiler.h>
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#include <configs/presidio_asic.h>
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#include <linux/psci.h>
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#include <asm/psci.h>
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#include <cpu_func.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CA_PERIPH_BASE 0xE0000000UL
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#define CA_PERIPH_SIZE 0x20000000UL
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#define CA_GLOBAL_BASE 0xf4320000
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#define CA_GLOBAL_JTAG_ID 0xf4320000
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#define CA_GLOBAL_BLOCK_RESET 0xf4320004
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#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16)
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#define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94
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#define CA_DMA_SEC_SSP_ID 0xf7001b80
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int print_cpuinfo(void)
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{
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printf("CPU: Cortina Presidio G3\n");
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return 0;
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}
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static struct mm_region presidio_mem_map[] = {
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{
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.virt = DDR_BASE,
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.phys = DDR_BASE,
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.size = PHYS_SDRAM_1_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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},
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{
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.virt = CA_PERIPH_BASE,
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.phys = CA_PERIPH_BASE,
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.size = CA_PERIPH_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = presidio_mem_map;
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static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
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u64 arg2)
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{
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asm volatile("mov x0, %0\n"
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"mov x1, %1\n"
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"mov x2, %2\n"
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"mov x3, %3\n"
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"smc #0\n"
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: "+r" (function_id)
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: "r" (arg0), "r" (arg1), "r" (arg2)
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);
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return function_id;
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}
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int board_early_init_r(void)
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{
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dcache_disable();
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return 0;
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}
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int board_init(void)
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{
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unsigned int reg_data, jtag_id;
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/* Enable timer */
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writel(1, CONFIG_SYS_TIMER_BASE);
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/* Enable snoop in CCI400 slave port#4 */
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writel(3, 0xF5595000);
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jtag_id = readl(CA_GLOBAL_JTAG_ID);
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/* If this is HGU variant then do not use
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* the Saturn daughter card ref. clk
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*/
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if (jtag_id == 0x1010D8F3) {
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reg_data = readl(0xF3100064);
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/* change multifunc. REF CLK pin to
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* a simple GPIO pin
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*/
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reg_data |= (1 << 1);
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writel(reg_data, 0xf3100064);
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}
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return 0;
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}
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int dram_init(void)
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{
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unsigned int ddr_size;
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ddr_size = readl(0x111100c);
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gd->ram_size = ddr_size * 0x100000;
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return 0;
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}
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void reset_cpu(void)
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{
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invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
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}
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#ifdef CONFIG_LAST_STAGE_INIT
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int last_stage_init(void)
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{
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u32 val;
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val = readl(CA_GLOBAL_BLOCK_RESET);
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val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA;
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writel(val, CA_GLOBAL_BLOCK_RESET);
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/* reduce output pclk ~3.7Hz to save power consumption */
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writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL);
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return 0;
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}
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#endif
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