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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
230 lines
4.6 KiB
C
230 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 Imagination Technologies
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*/
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#include <common.h>
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#include <ide.h>
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#include <netdev.h>
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#include <pci.h>
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#include <pci_gt64120.h>
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#include <pci_msc01.h>
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#include <rtc.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/malta.h>
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#include "superio.h"
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DECLARE_GLOBAL_DATA_PTR;
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enum core_card {
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CORE_UNKNOWN,
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CORE_LV,
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CORE_FPGA6,
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};
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enum sys_con {
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SYSCON_UNKNOWN,
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SYSCON_GT64120,
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SYSCON_MSC01,
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};
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static void malta_lcd_puts(const char *str)
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{
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int i;
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void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
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/* print up to 8 characters of the string */
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for (i = 0; i < min((int)strlen(str), 8); i++) {
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__raw_writel(str[i], reg);
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reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
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}
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/* fill the rest of the display with spaces */
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for (; i < 8; i++) {
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__raw_writel(' ', reg);
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reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
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}
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}
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static enum core_card malta_core_card(void)
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{
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u32 corid, rev;
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const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
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rev = __raw_readl(reg);
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corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
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switch (corid) {
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case MALTA_REVISION_CORID_CORE_LV:
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return CORE_LV;
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case MALTA_REVISION_CORID_CORE_FPGA6:
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return CORE_FPGA6;
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default:
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return CORE_UNKNOWN;
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}
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}
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static enum sys_con malta_sys_con(void)
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{
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switch (malta_core_card()) {
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case CORE_LV:
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return SYSCON_GT64120;
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case CORE_FPGA6:
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return SYSCON_MSC01;
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default:
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return SYSCON_UNKNOWN;
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}
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_MEM_SIZE;
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return 0;
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}
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int checkboard(void)
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{
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enum core_card core;
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malta_lcd_puts("U-Boot");
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puts("Board: MIPS Malta");
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core = malta_core_card();
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switch (core) {
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case CORE_LV:
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puts(" CoreLV");
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break;
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case CORE_FPGA6:
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puts(" CoreFPGA6");
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break;
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default:
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puts(" CoreUnknown");
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}
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putc('\n');
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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void _machine_restart(void)
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{
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void __iomem *reset_base;
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reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
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__raw_writel(GORESET, reset_base);
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mdelay(1000);
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}
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int board_early_init_f(void)
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{
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ulong io_base;
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/* choose correct PCI I/O base */
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switch (malta_sys_con()) {
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case SYSCON_GT64120:
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io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
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break;
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case SYSCON_MSC01:
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io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
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break;
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default:
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return -1;
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}
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set_io_port_base(io_base);
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/* setup FDC37M817 super I/O controller */
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malta_superio_init();
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return 0;
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}
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int misc_init_r(void)
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{
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rtc_reset();
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return 0;
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}
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void pci_init_board(void)
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{
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pci_dev_t bdf;
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u32 val32;
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u8 val8;
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switch (malta_sys_con()) {
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case SYSCON_GT64120:
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gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
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0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
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0x10000000, 0x10000000, 128 * 1024 * 1024,
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0x00000000, 0x00000000, 0x20000);
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break;
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default:
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case SYSCON_MSC01:
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msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
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0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
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MALTA_MSC01_PCIMEM_MAP,
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CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
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MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
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0x00000000, MALTA_MSC01_PCIIO_SIZE);
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break;
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}
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bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82371AB_0, 0);
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if (bdf == -1)
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panic("Failed to find PIIX4 PCI bridge\n");
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/* setup PCI interrupt routing */
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pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
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pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
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pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
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pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
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/* mux SERIRQ onto SERIRQ pin */
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pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
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val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
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pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
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/* enable SERIRQ - Linux currently depends upon this */
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pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
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val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
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pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
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bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82371AB, 0);
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if (bdf == -1)
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panic("Failed to find PIIX4 IDE controller\n");
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/* enable bus master & IO access */
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val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config_dword(bdf, PCI_COMMAND, val32);
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/* set latency */
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pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
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/* enable IDE/ATA */
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pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
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PCI_CFG_PIIX4_IDETIM_IDE);
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pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
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PCI_CFG_PIIX4_IDETIM_IDE);
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}
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