mirror of
https://github.com/brain-hackers/u-boot-brain
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5ff093ab9e
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
93 lines
1.3 KiB
C
93 lines
1.3 KiB
C
/*
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* Copyright (c) 2015 Google, Inc
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*
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* Copyright 2014 Rockchip Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_RK3288_SDRAM_H__
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#define _ASM_ARCH_RK3288_SDRAM_H__
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enum {
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DDR3 = 3,
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LPDDR3 = 6,
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UNUSED = 0xFF,
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};
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struct rk3288_sdram_channel {
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u8 rank;
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u8 col;
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u8 bk;
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u8 bw;
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u8 dbw;
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u8 row_3_4;
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u8 cs0_row;
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u8 cs1_row;
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};
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struct rk3288_sdram_pctl_timing {
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u32 togcnt1u;
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u32 tinit;
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u32 trsth;
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u32 togcnt100n;
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u32 trefi;
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u32 tmrd;
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u32 trfc;
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u32 trp;
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u32 trtw;
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u32 tal;
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u32 tcl;
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u32 tcwl;
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u32 tras;
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u32 trc;
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u32 trcd;
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u32 trrd;
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u32 trtp;
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u32 twr;
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u32 twtr;
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u32 texsr;
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u32 txp;
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u32 txpdll;
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u32 tzqcs;
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u32 tzqcsi;
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u32 tdqs;
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u32 tcksre;
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u32 tcksrx;
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u32 tcke;
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u32 tmod;
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u32 trstl;
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u32 tzqcl;
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u32 tmrr;
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u32 tckesr;
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u32 tdpd;
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};
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check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
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struct rk3288_sdram_phy_timing {
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u32 dtpr0;
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u32 dtpr1;
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u32 dtpr2;
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u32 mr[4];
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};
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struct rk3288_base_params {
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u32 noc_timing;
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u32 noc_activate;
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u32 ddrconfig;
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u32 ddr_freq;
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u32 dramtype;
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u32 stride;
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u32 odt;
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};
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struct rk3288_sdram_params {
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struct rk3288_sdram_channel ch[2];
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struct rk3288_sdram_pctl_timing pctl_timing;
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struct rk3288_sdram_phy_timing phy_timing;
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struct rk3288_base_params base;
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int num_channels;
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};
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#endif
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