Simon Goldschmidt d6d383ca27 arm: socfpga: provide default SPL_SIZE_LIMIT for gen5 ... This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>		2019-06-14 12:41:26 +02:00
..
include/mach	ARM: socfpga: Pull PL310 clearing into common code	2019-05-24 00:01:08 +02:00
board.c
clock_manager_arria10.c
clock_manager_gen5.c
clock_manager_s10.c
clock_manager.c
fpga_manager.c
freeze_controller.c
Kconfig	arm: socfpga: provide default SPL_SIZE_LIMIT for gen5	2019-06-14 12:41:26 +02:00
mailbox_s10.c	arm: socfpga: mailbox: Fix off-by-one error on command length checking	2019-04-25 00:00:49 +02:00
Makefile
misc_arria10.c	ARM: socfpga: Add support for selecting bridges in bridge command	2019-04-29 10:08:56 +02:00
misc_gen5.c	ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()	2019-04-29 10:33:45 +02:00
misc_s10.c	ARM: socfpga: stratix10: Probe FPGA status before bridge enable	2019-05-06 12:44:45 +02:00
misc.c	ARM: socfpga: Pull PL310 clearing into common code	2019-05-24 00:01:08 +02:00
mmu-arm64_s10.c
pinmux_arria10.c
qts-filter.sh
reset_manager_arria10.c
reset_manager_gen5.c	arm: socfpga: remove re-added ad-hoc reset code	2019-05-14 19:52:38 +02:00
reset_manager_s10.c	arm: sofcpga: s10: remove unused ad-hoc reset code	2019-05-14 19:52:39 +02:00
reset_manager.c
scan_manager.c
spl_a10.c	ARM: socfpga: Clear PL310 early in SPL	2019-05-24 00:01:08 +02:00
spl_gen5.c	ARM: socfpga: Pull PL310 clearing into common code	2019-05-24 00:01:08 +02:00
spl_s10.c	arm: socfpga: Move Stratix 10 SDRAM driver to DM	2019-05-06 12:44:17 +02:00
system_manager_gen5.c
system_manager_s10.c
timer_s10.c
timer.c
wrap_iocsr_config.c
wrap_pinmux_config_s10.c
wrap_pinmux_config.c
wrap_pll_config_s10.c
wrap_pll_config.c
wrap_sdram_config.c	arm: socfpga: make config structs const	2018-11-29 12:45:15 +01:00