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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
177 lines
4.3 KiB
C
177 lines
4.3 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* From Coreboot soc/intel/broadwell/include/soc/pei_data.h
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*
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* Copyright (C) 2014 Google Inc.
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*/
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#ifndef ASM_ARCH_PEI_DATA_H
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#define ASM_ARCH_PEI_DATA_H
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#include <linux/linkage.h>
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#define PEI_VERSION 22
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typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
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enum board_type {
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BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
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BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
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BOARD_TYPE_USER1, /* SV mobile */
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BOARD_TYPE_USER2, /* SV desktop */
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BOARD_TYPE_USER3, /* SV server */
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BOARD_TYPE_ULT, /* ULT */
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BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
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BOARD_TYPE_UNKNOWN,
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};
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#define MAX_USB2_PORTS 14
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#define MAX_USB3_PORTS 6
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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USB_PORT_BACK_PANEL = 0,
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USB_PORT_FRONT_PANEL,
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USB_PORT_DOCK,
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USB_PORT_MINI_PCIE,
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USB_PORT_FLEX,
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USB_PORT_INTERNAL,
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USB_PORT_SKIP,
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USB_PORT_NGFF_DEVICE_DOWN,
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};
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struct usb2_port_setting {
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/*
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* Usb Port Length:
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* [16:4] = length in inches in octal format
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* [3:0] = decimal point
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*/
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uint16_t length;
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uint8_t enable;
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uint8_t oc_pin;
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uint8_t location;
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} __packed;
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struct usb3_port_setting {
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uint8_t enable;
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uint8_t oc_pin;
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/*
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* Set to 0 if trace length is > 5 inches
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* Set to 1 if trace length is <= 5 inches
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*/
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uint8_t fixed_eq;
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} __packed;
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struct pei_data {
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uint32_t pei_version;
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enum board_type board_type;
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int boot_mode;
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int ec_present;
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int usbdebug;
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/* Base addresses */
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uint32_t pciexbar;
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uint16_t smbusbar;
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uint32_t xhcibar;
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uint32_t ehcibar;
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uint32_t gttbar;
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uint32_t rcba;
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uint32_t pmbase;
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uint32_t gpiobase;
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uint32_t temp_mmio_base;
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uint32_t tseg_size;
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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int dimm_channel0_disabled;
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int dimm_channel1_disabled;
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/* Set to 0 for memory down */
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uint8_t spd_addresses[4];
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/* Enable 2x Refresh Mode */
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int ddr_refresh_2x;
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/* DQ pins are interleaved on board */
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int dq_pins_interleaved;
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/* Limit DDR3 frequency */
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int max_ddr3_freq;
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/* Disable self refresh */
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int disable_self_refresh;
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/* Disable cmd power/CKEPD */
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int disable_cmd_pwr;
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/* USB port configuration */
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
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/*
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* USB3 board specific PHY tuning
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*/
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/* Valid range: 0x69 - 0x80 */
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uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
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/* Valid range: 0x80 - 0x9c */
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uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
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/* Valid range: 0x39 - 0x80 */
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uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
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/* Valid range: 0x3d - 0x4a */
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uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
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/* Console output function */
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tx_byte_func tx_byte;
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/*
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* DIMM SPD data for memory down configurations
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* [CHANNEL][SLOT][SPD]
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*/
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uint8_t spd_data[2][2][512];
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/*
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* LPDDR3 DQ byte map
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* [CHANNEL][ITERATION][2]
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*
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* Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
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* DQByteMap[0] - ClkDQByteMap:
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* - If clock is per rank, program to [0xFF, 0xFF]
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* - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
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* - If clock is shared by 2 ranks but does not go to all bytes,
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* Entry[i] defines which DQ bytes Group i services
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* DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
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* DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
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* DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
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* For DDR, DQByteMap[3:1] = [0xFF, 0]
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* DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
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* since we have 1 CTL / rank
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* DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
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* since we have 1 CA Vref
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*/
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uint8_t dq_map[2][6][2];
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/*
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* LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
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* [CHANNEL][MAX_BYTES]
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*/
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uint8_t dqs_map[2][8];
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/* Data read from flash and passed into MRC */
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const void *saved_data;
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int saved_data_size;
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/* Disable use of saved data (can be set by mainboard) */
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int disable_saved_data;
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/* Data from MRC that should be saved to flash */
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void *data_to_save;
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int data_to_save_size;
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struct pei_memory_info meminfo;
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} __packed;
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void mainboard_fill_pei_data(struct pei_data *pei_data);
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void broadwell_fill_pei_data(struct pei_data *pei_data);
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#endif
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