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https://github.com/brain-hackers/u-boot-brain
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8c59f2023c
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly jumping to the image and via OpenSBI firmware. In the first case, both U-Boot SPL and proper must be compiled to run in the same privilege mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine mode and U-Boot proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
83 lines
1.3 KiB
Plaintext
83 lines
1.3 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Based on arch/riscv/cpu/u-boot.lds, which is
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*
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* and arch/mips/cpu/u-boot-spl.lds.
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*/
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MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
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MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
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LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
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OUTPUT_ARCH("riscv")
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ENTRY(_start)
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SECTIONS
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{
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. = ALIGN(4);
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.text : {
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arch/riscv/cpu/start.o (.text)
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*(.text*)
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} > .spl_mem
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. = ALIGN(4);
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.rodata : {
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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} > .spl_mem
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. = ALIGN(4);
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.data : {
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*(.data*)
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} > .spl_mem
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. = ALIGN(4);
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.got : {
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__got_start = .;
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*(.got.plt) *(.got)
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__got_end = .;
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} > .spl_mem
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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} > .spl_mem
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. = ALIGN(4);
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.binman_sym_table : {
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__binman_sym_start = .;
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KEEP(*(SORT(.binman_sym*)));
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__binman_sym_end = .;
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} > .spl_mem
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. = ALIGN(4);
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/DISCARD/ : { *(.rela.plt*) }
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.rela.dyn : {
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__rel_dyn_start = .;
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*(.rela*)
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__rel_dyn_end = .;
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} > .spl_mem
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. = ALIGN(4);
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.dynsym : {
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__dyn_sym_start = .;
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*(.dynsym)
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__dyn_sym_end = .;
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} > .spl_mem
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. = ALIGN(4);
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_end = .;
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.bss : {
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__bss_start = .;
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*(.bss*)
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. = ALIGN(4);
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__bss_end = .;
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} > .bss_mem
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}
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