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https://github.com/brain-hackers/u-boot-brain
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358032f9a5
Add DT node for HyperBus Memory Controller in the FSS. On J721e, its not possible to use OSPI0 and HBMC simultaneously as they are muxed within the Flash Subsystem hence disable HBMC by default as keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash instead of OSPI. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
137 lines
3.3 KiB
Plaintext
137 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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dmsc: dmsc@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x0 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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ti,scan-clocks-from-dt;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 287 0>;
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clock-names = "fclk";
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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};
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mcu_r5fss0: r5fss@41000000 {
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compatible = "ti,j721e-r5fss";
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lockstep-mode = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x41000000 0x00 0x41000000 0x20000>,
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<0x41400000 0x00 0x41400000 0x20000>;
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power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
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mcu_r5fss0_core0: r5f@41000000 {
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compatible = "ti,j721e-r5f";
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reg = <0x41000000 0x00008000>,
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<0x41010000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <250>;
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ti,sci-proc-ids = <0x01 0xFF>;
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resets = <&k3_reset 250 1>;
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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mcu_r5fss0_core1: r5f@41400000 {
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compatible = "ti,j721e-r5f";
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reg = <0x41400000 0x00008000>,
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<0x41410000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <251>;
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ti,sci-proc-ids = <0x02 0xFF>;
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resets = <&k3_reset 251 1>;
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atcm-enable = <1>;
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btcm-enable = <1>;
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loczrama = <1>;
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};
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};
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fss: fss@47000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x47000000 0x0 0x100>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hbmc_mux: hbmc-mux {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4 0x2>; /* HBMC select */
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};
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hbmc: hyperbus@47034000 {
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compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
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reg = <0x0 0x47034000 0x0 0x100>,
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<0x5 0x00000000 0x1 0x0000000>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <2>;
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#size-cells = <1>;
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mux-controls = <&hbmc_mux 0>;
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assigned-clocks = <&k3_clks 102 0>;
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assigned-clock-rates = <250000000>;
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};
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};
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};
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