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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
480 lines
12 KiB
C
480 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 SiFive, Inc.
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* Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
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*
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* SiFive SPI controller driver (master mode only)
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <malloc.h>
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#include <spi-mem.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <linux/log2.h>
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#include <clk.h>
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#define SIFIVE_SPI_MAX_CS 32
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#define SIFIVE_SPI_DEFAULT_DEPTH 8
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#define SIFIVE_SPI_DEFAULT_BITS 8
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/* register offsets */
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#define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
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#define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
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#define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
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#define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
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#define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
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#define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
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#define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
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#define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
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#define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
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#define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
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#define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
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#define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
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#define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
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#define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
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#define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
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#define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
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/* sckdiv bits */
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#define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
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/* sckmode bits */
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#define SIFIVE_SPI_SCKMODE_PHA BIT(0)
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#define SIFIVE_SPI_SCKMODE_POL BIT(1)
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#define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
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SIFIVE_SPI_SCKMODE_POL)
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/* csmode bits */
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#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
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#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
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#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
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/* delay0 bits */
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#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
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#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
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#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
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/* delay1 bits */
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#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
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#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
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#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
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/* fmt bits */
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#define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
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#define SIFIVE_SPI_FMT_PROTO_DUAL 1U
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#define SIFIVE_SPI_FMT_PROTO_QUAD 2U
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#define SIFIVE_SPI_FMT_PROTO_MASK 3U
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#define SIFIVE_SPI_FMT_ENDIAN BIT(2)
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#define SIFIVE_SPI_FMT_DIR BIT(3)
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#define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
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/* txdata bits */
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#define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
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#define SIFIVE_SPI_TXDATA_FULL BIT(31)
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/* rxdata bits */
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#define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
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#define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
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/* ie and ip bits */
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#define SIFIVE_SPI_IP_TXWM BIT(0)
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#define SIFIVE_SPI_IP_RXWM BIT(1)
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/* format protocol */
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#define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */
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#define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */
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#define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */
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struct sifive_spi {
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void *regs; /* base address of the registers */
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u32 fifo_depth;
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u32 bits_per_word;
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u32 cs_inactive; /* Level of the CS pins when inactive*/
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u32 freq;
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u32 num_cs;
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u8 fmt_proto;
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};
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static void sifive_spi_prep_device(struct sifive_spi *spi,
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struct dm_spi_slave_platdata *slave_plat)
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{
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/* Update the chip select polarity */
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if (slave_plat->mode & SPI_CS_HIGH)
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spi->cs_inactive &= ~BIT(slave_plat->cs);
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else
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spi->cs_inactive |= BIT(slave_plat->cs);
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writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
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/* Select the correct device */
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writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
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}
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static int sifive_spi_set_cs(struct sifive_spi *spi,
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struct dm_spi_slave_platdata *slave_plat)
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{
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u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
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if (slave_plat->mode & SPI_CS_HIGH)
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cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
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writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
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return 0;
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}
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static void sifive_spi_clear_cs(struct sifive_spi *spi)
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{
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writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
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}
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static void sifive_spi_prep_transfer(struct sifive_spi *spi,
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struct dm_spi_slave_platdata *slave_plat,
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u8 *rx_ptr)
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{
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u32 cr;
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/* Modify the SPI protocol mode */
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cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
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/* Bits per word ? */
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cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
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cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
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/* LSB first? */
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cr &= ~SIFIVE_SPI_FMT_ENDIAN;
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if (slave_plat->mode & SPI_LSB_FIRST)
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cr |= SIFIVE_SPI_FMT_ENDIAN;
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/* Number of wires ? */
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cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
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switch (spi->fmt_proto) {
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case SIFIVE_SPI_PROTO_QUAD:
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cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
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break;
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case SIFIVE_SPI_PROTO_DUAL:
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cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
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break;
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default:
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cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
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break;
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}
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/* SPI direction in/out ? */
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cr &= ~SIFIVE_SPI_FMT_DIR;
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if (!rx_ptr)
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cr |= SIFIVE_SPI_FMT_DIR;
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writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
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}
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static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
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{
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u32 data;
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do {
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data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
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} while (data & SIFIVE_SPI_RXDATA_EMPTY);
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if (rx_ptr)
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*rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
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}
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static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
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{
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u32 data;
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u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
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SIFIVE_SPI_TXDATA_DATA_MASK;
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do {
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data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
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} while (data & SIFIVE_SPI_TXDATA_FULL);
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writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
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}
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static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
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{
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return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
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bit, true, 100, false);
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}
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static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct sifive_spi *spi = dev_get_priv(bus);
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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const u8 *tx_ptr = dout;
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u8 *rx_ptr = din;
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u32 remaining_len;
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int ret;
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if (flags & SPI_XFER_BEGIN) {
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sifive_spi_prep_device(spi, slave_plat);
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ret = sifive_spi_set_cs(spi, slave_plat);
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if (ret)
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return ret;
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}
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sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
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remaining_len = bitlen / 8;
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while (remaining_len) {
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unsigned int n_words = min(remaining_len, spi->fifo_depth);
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unsigned int tx_words, rx_words;
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/* Enqueue n_words for transmission */
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for (tx_words = 0; tx_words < n_words; tx_words++) {
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if (!tx_ptr)
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sifive_spi_tx(spi, NULL);
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else
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sifive_spi_tx(spi, tx_ptr++);
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}
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if (rx_ptr) {
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/* Wait for transmission + reception to complete */
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writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
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ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
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if (ret)
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return ret;
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/* Read out all the data from the RX FIFO */
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for (rx_words = 0; rx_words < n_words; rx_words++)
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sifive_spi_rx(spi, rx_ptr++);
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} else {
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/* Wait for transmission to complete */
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ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
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if (ret)
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return ret;
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}
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remaining_len -= n_words;
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}
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if (flags & SPI_XFER_END)
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sifive_spi_clear_cs(spi);
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return 0;
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}
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static int sifive_spi_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *dev = slave->dev;
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struct sifive_spi *spi = dev_get_priv(dev->parent);
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unsigned long flags = SPI_XFER_BEGIN;
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u8 opcode = op->cmd.opcode;
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unsigned int pos = 0;
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const void *tx_buf = NULL;
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void *rx_buf = NULL;
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int op_len, i;
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int ret;
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if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
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flags |= SPI_XFER_END;
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spi->fmt_proto = op->cmd.buswidth;
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/* send the opcode */
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ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
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if (ret < 0) {
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dev_err(dev, "failed to xfer opcode\n");
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return ret;
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}
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op_len = op->addr.nbytes + op->dummy.nbytes;
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u8 op_buf[op_len];
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/* send the addr + dummy */
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if (op->addr.nbytes) {
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/* fill address */
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for (i = 0; i < op->addr.nbytes; i++)
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op_buf[pos + i] = op->addr.val >>
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(8 * (op->addr.nbytes - i - 1));
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pos += op->addr.nbytes;
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/* fill dummy */
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if (op->dummy.nbytes)
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memset(op_buf + pos, 0xff, op->dummy.nbytes);
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/* make sure to set end flag, if no data bytes */
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if (!op->data.nbytes)
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flags |= SPI_XFER_END;
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spi->fmt_proto = op->addr.buswidth;
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ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
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if (ret < 0) {
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dev_err(dev, "failed to xfer addr + dummy\n");
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return ret;
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}
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}
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/* send/received the data */
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_IN)
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rx_buf = op->data.buf.in;
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else
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tx_buf = op->data.buf.out;
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spi->fmt_proto = op->data.buswidth;
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ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
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tx_buf, rx_buf, SPI_XFER_END);
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if (ret) {
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dev_err(dev, "failed to xfer data\n");
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return ret;
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}
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}
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return 0;
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}
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static int sifive_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct sifive_spi *spi = dev_get_priv(bus);
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u32 scale;
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if (speed > spi->freq)
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speed = spi->freq;
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/* Cofigure max speed */
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scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
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& SIFIVE_SPI_SCKDIV_DIV_MASK;
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writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
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return 0;
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}
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static int sifive_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct sifive_spi *spi = dev_get_priv(bus);
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u32 cr;
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/* Switch clock mode bits */
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cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
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~SIFIVE_SPI_SCKMODE_MODE_MASK;
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if (mode & SPI_CPHA)
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cr |= SIFIVE_SPI_SCKMODE_PHA;
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if (mode & SPI_CPOL)
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cr |= SIFIVE_SPI_SCKMODE_POL;
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writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
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return 0;
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}
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static int sifive_spi_cs_info(struct udevice *bus, uint cs,
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struct spi_cs_info *info)
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{
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struct sifive_spi *spi = dev_get_priv(bus);
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if (cs >= spi->num_cs)
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return -EINVAL;
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return 0;
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}
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static void sifive_spi_init_hw(struct sifive_spi *spi)
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{
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u32 cs_bits;
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/* probe the number of CS lines */
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spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
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writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
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cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
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writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
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if (!cs_bits) {
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printf("Could not auto probe CS lines\n");
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return;
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}
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spi->num_cs = ilog2(cs_bits) + 1;
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if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
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printf("Invalid number of spi slaves\n");
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return;
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}
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/* Watermark interrupts are disabled by default */
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writel(0, spi->regs + SIFIVE_SPI_REG_IE);
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/* Default watermark FIFO threshold values */
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writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
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writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
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/* Set CS/SCK Delays and Inactive Time to defaults */
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writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
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spi->regs + SIFIVE_SPI_REG_DELAY0);
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writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
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spi->regs + SIFIVE_SPI_REG_DELAY1);
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/* Exit specialized memory-mapped SPI flash mode */
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writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
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}
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static int sifive_spi_probe(struct udevice *bus)
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{
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struct sifive_spi *spi = dev_get_priv(bus);
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struct clk clkdev;
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int ret;
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spi->regs = (void *)(ulong)dev_remap_addr(bus);
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if (!spi->regs)
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return -ENODEV;
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spi->fifo_depth = dev_read_u32_default(bus,
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"sifive,fifo-depth",
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SIFIVE_SPI_DEFAULT_DEPTH);
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spi->bits_per_word = dev_read_u32_default(bus,
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"sifive,max-bits-per-word",
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SIFIVE_SPI_DEFAULT_BITS);
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ret = clk_get_by_index(bus, 0, &clkdev);
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if (ret)
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return ret;
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spi->freq = clk_get_rate(&clkdev);
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/* init the sifive spi hw */
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sifive_spi_init_hw(spi);
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return 0;
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}
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static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
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.exec_op = sifive_spi_exec_op,
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};
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static const struct dm_spi_ops sifive_spi_ops = {
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.xfer = sifive_spi_xfer,
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.set_speed = sifive_spi_set_speed,
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.set_mode = sifive_spi_set_mode,
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.cs_info = sifive_spi_cs_info,
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.mem_ops = &sifive_spi_mem_ops,
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};
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static const struct udevice_id sifive_spi_ids[] = {
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{ .compatible = "sifive,spi0" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(sifive_spi) = {
|
|
.name = "sifive_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = sifive_spi_ids,
|
|
.ops = &sifive_spi_ops,
|
|
.priv_auto_alloc_size = sizeof(struct sifive_spi),
|
|
.probe = sifive_spi_probe,
|
|
};
|