mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
313 lines
7.7 KiB
C
313 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2013 - 2018 Xilinx, Michal Simek
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*/
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <linux/list.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <dm.h>
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#include <dt-bindings/gpio/gpio.h>
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#define XILINX_GPIO_MAX_BANK 2
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/* Gpio simple map */
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struct gpio_regs {
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u32 gpiodata;
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u32 gpiodir;
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};
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struct xilinx_gpio_platdata {
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struct gpio_regs *regs;
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int bank_max[XILINX_GPIO_MAX_BANK];
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int bank_input[XILINX_GPIO_MAX_BANK];
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int bank_output[XILINX_GPIO_MAX_BANK];
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u32 dout_default[XILINX_GPIO_MAX_BANK];
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};
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struct xilinx_gpio_privdata {
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u32 output_val[XILINX_GPIO_MAX_BANK];
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};
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static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
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u32 *bank_pin_num, struct udevice *dev)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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u32 bank, max_pins;
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/* the first gpio is 0 not 1 */
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u32 pin_num = offset;
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for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
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max_pins = platdata->bank_max[bank];
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if (pin_num < max_pins) {
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debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
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bank, pin_num);
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*bank_num = bank;
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*bank_pin_num = pin_num;
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return 0;
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}
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pin_num -= max_pins;
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}
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return -EINVAL;
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}
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static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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val = priv->output_val[bank];
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debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
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__func__, (ulong)platdata->regs, value, offset, bank, pin, val);
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if (value)
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val = val | (1 << pin);
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else
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val = val & ~(1 << pin);
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writel(val, &platdata->regs->gpiodata + bank * 2);
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priv->output_val[bank] = val;
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return 0;
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};
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static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
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(ulong)platdata->regs, offset, bank, pin);
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if (platdata->bank_output[bank]) {
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debug("%s: Read saved output value\n", __func__);
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val = priv->output_val[bank];
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} else {
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debug("%s: Read input value from reg\n", __func__);
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val = readl(&platdata->regs->gpiodata + bank * 2);
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}
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val = !!(val & (1 << pin));
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return val;
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};
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static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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/* Check if all pins are inputs */
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if (platdata->bank_input[bank])
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return GPIOF_INPUT;
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/* Check if all pins are outputs */
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if (platdata->bank_output[bank])
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return GPIOF_OUTPUT;
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/* FIXME test on dual */
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val = readl(&platdata->regs->gpiodir + bank * 2);
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val = !(val & (1 << pin));
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/* input is 1 in reg but GPIOF_INPUT is 0 */
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/* output is 0 in reg but GPIOF_OUTPUT is 1 */
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return val;
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}
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static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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/* can't change it if all is input by default */
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if (platdata->bank_input[bank])
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return -EINVAL;
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xilinx_gpio_set_value(dev, offset, value);
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if (!platdata->bank_output[bank]) {
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val = readl(&platdata->regs->gpiodir + bank * 2);
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val = val & ~(1 << pin);
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writel(val, &platdata->regs->gpiodir + bank * 2);
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}
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return 0;
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}
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static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int val, ret;
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u32 bank, pin;
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ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
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if (ret)
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return ret;
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/* Already input */
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if (platdata->bank_input[bank])
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return 0;
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/* can't change it if all is output by default */
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if (platdata->bank_output[bank])
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return -EINVAL;
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val = readl(&platdata->regs->gpiodir + bank * 2);
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val = val | (1 << pin);
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writel(val, &platdata->regs->gpiodir + bank * 2);
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return 0;
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}
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static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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desc->offset = args->args[0];
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debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
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args->args_count, args->args[0], args->args[1], args->args[2]);
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/*
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* The second cell is channel offset:
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* 0 is first channel, 8 is second channel
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*
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* U-Boot driver just combine channels together that's why simply
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* add amount of pins in second channel if present.
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*/
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if (args->args[1]) {
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if (!platdata->bank_max[1]) {
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printf("%s: %s has no second channel\n",
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__func__, dev->name);
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return -EINVAL;
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}
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desc->offset += platdata->bank_max[0];
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}
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/* The third cell is optional */
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if (args->args_count > 2)
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desc->flags = (args->args[2] &
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GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
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debug("%s: offset %x, flags %lx\n",
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__func__, desc->offset, desc->flags);
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return 0;
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}
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static const struct dm_gpio_ops xilinx_gpio_ops = {
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.direction_input = xilinx_gpio_direction_input,
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.direction_output = xilinx_gpio_direction_output,
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.get_value = xilinx_gpio_get_value,
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.set_value = xilinx_gpio_set_value,
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.get_function = xilinx_gpio_get_function,
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.xlate = xilinx_gpio_xlate,
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};
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static int xilinx_gpio_probe(struct udevice *dev)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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const void *label_ptr;
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label_ptr = dev_read_prop(dev, "label", NULL);
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if (label_ptr) {
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uc_priv->bank_name = strdup(label_ptr);
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if (!uc_priv->bank_name)
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return -ENOMEM;
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} else {
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uc_priv->bank_name = dev->name;
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}
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uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
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priv->output_val[0] = platdata->dout_default[0];
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if (platdata->bank_max[1])
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priv->output_val[1] = platdata->dout_default[1];
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return 0;
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}
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static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
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{
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struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
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int is_dual;
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platdata->regs = (struct gpio_regs *)dev_read_addr(dev);
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platdata->bank_max[0] = dev_read_u32_default(dev,
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"xlnx,gpio-width", 0);
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platdata->bank_input[0] = dev_read_u32_default(dev,
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"xlnx,all-inputs", 0);
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platdata->bank_output[0] = dev_read_u32_default(dev,
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"xlnx,all-outputs", 0);
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platdata->dout_default[0] = dev_read_u32_default(dev,
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"xlnx,dout-default",
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0);
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is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
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if (is_dual) {
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platdata->bank_max[1] = dev_read_u32_default(dev,
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"xlnx,gpio2-width", 0);
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platdata->bank_input[1] = dev_read_u32_default(dev,
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"xlnx,all-inputs-2", 0);
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platdata->bank_output[1] = dev_read_u32_default(dev,
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"xlnx,all-outputs-2", 0);
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platdata->dout_default[1] = dev_read_u32_default(dev,
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"xlnx,dout-default-2", 0);
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}
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return 0;
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}
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static const struct udevice_id xilinx_gpio_ids[] = {
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{ .compatible = "xlnx,xps-gpio-1.00.a",},
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{ }
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};
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U_BOOT_DRIVER(xilinx_gpio) = {
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.name = "xlnx_gpio",
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.id = UCLASS_GPIO,
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.ops = &xilinx_gpio_ops,
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.of_match = xilinx_gpio_ids,
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.ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
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.probe = xilinx_gpio_probe,
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.platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
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.priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
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};
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