mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
35546f6f20
This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
44 lines
952 B
Plaintext
44 lines
952 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_SPL_DM=y
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CONFIG_DM_GPIO=y
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CONFIG_TARGET_SOCFPGA_IS1=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1"
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CONFIG_SPL=y
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CONFIG_SPL_STACK_R=y
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CONFIG_FIT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_GREPENV=y
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# CONFIG_CMD_MEMTEST is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_MMC is not set
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_USE_4K_SECTORS=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_SYS_NS16550=y
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CONFIG_CADENCE_QSPI=y
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