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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
168 lines
4.2 KiB
C
168 lines
4.2 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*
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* For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
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* tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
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* all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
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* For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
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* from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
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*
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* CPO value doesn't matter if workaround for errata 111 and 134 enabled.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 8, 7, 5, 0},
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{2, 400, 8, 9, 5, 0},
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{2, 549, 8, 11, 5, 0},
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{2, 680, 8, 10, 5, 0},
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{2, 850, 8, 12, 5, 1},
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{1, 333, 6, 7, 3, 0},
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{1, 400, 6, 9, 3, 0},
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{1, 549, 6, 11, 3, 0},
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{1, 680, 1, 10, 5, 0},
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{1, 850, 1, 12, 5, 0},
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{}
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};
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static const struct board_specific_parameters udimm1[] = {
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/*
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* memory controller 1
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 8, 7, 5, 0},
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{2, 400, 8, 9, 5, 0},
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{2, 549, 8, 11, 5, 0},
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{2, 680, 8, 11, 5, 0},
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{2, 850, 8, 13, 5, 1},
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{1, 333, 6, 7, 3, 0},
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{1, 400, 6, 9, 3, 0},
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{1, 549, 6, 11, 3, 0},
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{1, 680, 1, 11, 6, 0},
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{1, 850, 1, 13, 6, 0},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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udimm1,
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};
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static const struct board_specific_parameters rdimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 4, 7, 3, 0},
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{2, 400, 4, 9, 3, 0},
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{2, 549, 4, 11, 3, 0},
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{2, 680, 4, 10, 3, 0},
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{2, 850, 4, 12, 3, 1},
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{}
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};
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static const struct board_specific_parameters rdimm1[] = {
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/*
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* memory controller 1
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{2, 333, 4, 7, 3, 0},
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{2, 400, 4, 9, 3, 0},
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{2, 549, 4, 11, 3, 0},
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{2, 680, 4, 11, 3, 0},
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{2, 850, 4, 13, 3, 1},
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{}
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};
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static const struct board_specific_parameters *rdimms[] = {
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rdimm0,
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rdimm1,
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 1) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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if (popts->registered_dimm_en)
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pbsp = rdimms[ctrl_num];
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else
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pbsp = udimms[ctrl_num];
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->twot_en = pbsp->force_2t;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found "
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"for data rate %lu MT/s!\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->twot_en = pbsp->force_2t;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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}
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