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https://github.com/brain-hackers/u-boot-brain
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![Mingkai Hu](/assets/img/avatar_default.png)
LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
137 lines
2.8 KiB
C
137 lines
2.8 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ppa.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
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u8 cfg_rcw_src1, cfg_rcw_src2;
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u16 cfg_rcw_src;
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u8 sd1refclk_sel;
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puts("Board: LS1046ARDB, boot from ");
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cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
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cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
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cpld_rev_bit(&cfg_rcw_src1);
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cfg_rcw_src = cfg_rcw_src1;
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cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
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if (cfg_rcw_src == 0x44)
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printf("QSPI vBank %d\n", CPLD_READ(vbank));
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else if (cfg_rcw_src == 0x40)
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puts("SD\n");
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else
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puts("Invalid setting of SW5\n");
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printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
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CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
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puts("SERDES Reference Clocks:\n");
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sd1refclk_sel = CPLD_READ(sd1refclk_sel);
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printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = initdram(0);
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return 0;
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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/* invert AQR105 IRQ pins polarity */
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out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
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return 0;
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}
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void config_board_mux(void)
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{
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 usb_pwrfault;
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/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */
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out_be32(&scfg->rcwpmuxcr0, 0x3300);
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out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
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usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB3_SHIFT) |
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(SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB2_SHIFT) |
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(SCFG_USBPWRFAULT_SHARED <<
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SCFG_USBPWRFAULT_USB1_SHIFT);
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out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
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#endif
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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config_board_mux();
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return 0;
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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/* fixup DT for the two DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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fdt_fixup_memory_banks(blob, base, size, 2);
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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#endif
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return 0;
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}
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