mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
c11599b473
The ipu node in imx53 is needed for DM_VIDEO. We also need to set u-boot,dm-pre-reloc to initialize before relocation. Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
425 lines
9.6 KiB
Plaintext
425 lines
9.6 KiB
Plaintext
/*
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* Copyright 2016 Beckhoff Automation
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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#include "imx53-pinfunc.h"
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#include <dt-bindings/clock/imx5-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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aliases {
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serial1 = &uart2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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ipu0 = &ipu;
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mmc0 = &esdhc1;
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mmc1 = &esdhc2;
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mmc2 = &esdhc3;
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mmc3 = &esdhc4;
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usb1 = &usbh1;
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};
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tzic: tz-interrupt-controller@fffc000 {
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compatible = "fsl,imx53-tzic", "fsl,tzic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x0fffc000 0x4000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&tzic>;
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ranges;
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u-boot,dm-pre-reloc;
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aips@50000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x10000000>;
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ranges;
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spba@50000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x40000>;
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ranges;
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esdhc1: esdhc@50004000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50004000 0x4000>;
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interrupts = <1>;
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clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC1_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc2: esdhc@50008000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50008000 0x4000>;
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interrupts = <2>;
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clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC2_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc3: esdhc@50020000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50020000 0x4000>;
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interrupts = <3>;
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clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC3_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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esdhc4: esdhc@50024000 {
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compatible = "fsl,imx53-esdhc";
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reg = <0x50024000 0x4000>;
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interrupts = <4>;
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clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
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<&clks IMX5_CLK_DUMMY>,
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<&clks IMX5_CLK_ESDHC4_PER_GATE>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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status = "disabled";
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};
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};
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iomuxc: iomuxc@53fa8000 {
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compatible = "fsl,imx53-iomuxc";
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reg = <0x53fa8000 0x4000>;
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};
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gpr: iomuxc-gpr@53fa8000 {
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compatible = "fsl,imx53-iomuxc-gpr", "syscon";
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reg = <0x53fa8000 0xc>;
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};
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uart2: serial@53fc0000 {
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compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
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reg = <0x53fc0000 0x4000>;
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interrupts = <32>;
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clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
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<&clks IMX5_CLK_UART2_PER_GATE>;
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clock-names = "ipg", "per";
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dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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usbh1: usb@53f80200 {
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compatible = "fsl,imx53-usb", "fsl,imx27-usb";
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reg = <0x53f80200 0x0200>;
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interrupts = <14>;
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clocks = <&clks IMX5_CLK_USBOH3_GATE>;
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dr_mode = "host";
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status = "disabled";
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};
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clks: ccm@53fd4000{
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compatible = "fsl,imx53-ccm";
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reg = <0x53fd4000 0x4000>;
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interrupts = <0 71 0x04 0 72 0x04>;
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#clock-cells = <1>;
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};
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gpio1: gpio@53f84000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f84000 0x4000>;
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interrupts = <50 51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@53f88000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f88000 0x4000>;
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interrupts = <52 53>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@53f8c000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f8c000 0x4000>;
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interrupts = <54 55>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@53f90000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53f90000 0x4000>;
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interrupts = <56 57>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@53fdc000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53fdc000 0x4000>;
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interrupts = <103 104>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@53fe0000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53fe0000 0x4000>;
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interrupts = <105 106>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio7: gpio@53fe4000 {
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compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
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reg = <0x53fe4000 0x4000>;
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interrupts = <107 108>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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i2c3: i2c@53fec000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
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reg = <0x53fec000 0x4000>;
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interrupts = <64>;
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clocks = <&clks IMX5_CLK_I2C3_GATE>;
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status = "disabled";
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};
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};
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aips@60000000 { /* AIPS2 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x60000000 0x10000000>;
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ranges;
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sdma: sdma@63fb0000 {
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compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
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reg = <0x63fb0000 0x4000>;
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interrupts = <6>;
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clocks = <&clks IMX5_CLK_SDMA_GATE>,
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<&clks IMX5_CLK_SDMA_GATE>;
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clock-names = "ipg", "ahb";
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#dma-cells = <3>;
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
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};
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fec: ethernet@63fec000 {
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compatible = "fsl,imx53-fec", "fsl,imx25-fec";
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reg = <0x63fec000 0x4000>;
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interrupts = <87>;
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clocks = <&clks IMX5_CLK_FEC_GATE>,
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<&clks IMX5_CLK_FEC_GATE>,
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<&clks IMX5_CLK_FEC_GATE>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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};
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i2c2: i2c@63fc4000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
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reg = <0x63fc4000 0x4000>;
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interrupts = <63>;
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clocks = <&clks IMX5_CLK_I2C2_GATE>;
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status = "disabled";
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};
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i2c1: i2c@63fc8000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
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reg = <0x63fc8000 0x4000>;
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interrupts = <62>;
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clocks = <&clks IMX5_CLK_I2C1_GATE>;
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status = "disabled";
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};
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};
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ipu: ipu@18000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ipu";
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reg = <0x18000000 0x08000000>;
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interrupts = <11 10>;
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clocks = <&clks IMX5_CLK_IPU_GATE>,
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<&clks IMX5_CLK_IPU_DI0_GATE>,
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<&clks IMX5_CLK_IPU_DI1_GATE>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 2>;
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u-boot,dm-pre-reloc;
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ipu_csi0: port@0 {
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reg = <0>;
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};
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ipu_csi1: port@1 {
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reg = <1>;
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};
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ipu_di0: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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ipu_di0_disp0: endpoint@0 {
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reg = <0>;
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};
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ipu_di0_lvds0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds0_in>;
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};
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};
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ipu_di1: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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ipu_di1_disp1: endpoint@0 {
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reg = <0>;
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};
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ipu_di1_lvds1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds1_in>;
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};
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ipu_di1_tve: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&tve_in>;
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};
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};
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};
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tve: tve@63ff0000 {
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compatible = "fsl,imx53-tve";
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reg = <0x63ff0000 0x1000>;
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interrupts = <92>;
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clocks = <&clks IMX5_CLK_TVE_GATE>,
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<&clks IMX5_CLK_IPU_DI1_SEL>;
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clock-names = "tve", "di_sel";
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status = "disabled";
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port {
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tve_in: endpoint {
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remote-endpoint = <&ipu_di1_tve>;
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};
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};
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};
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src: src@53fd0000 {
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compatible = "fsl,imx53-src", "fsl,imx51-src";
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reg = <0x53fd0000 0x4000>;
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#reset-cells = <1>;
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};
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ldb: ldb@53fa8008 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ldb";
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reg = <0x53fa8008 0x4>;
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gpr = <&gpr>;
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clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
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<&clks IMX5_CLK_LDB_DI1_SEL>,
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<&clks IMX5_CLK_IPU_DI0_SEL>,
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<&clks IMX5_CLK_IPU_DI1_SEL>,
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<&clks IMX5_CLK_LDB_DI0_GATE>,
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<&clks IMX5_CLK_LDB_DI1_GATE>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel",
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"di0", "di1";
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status = "disabled";
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lvds-channel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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status = "disabled";
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port@0 {
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reg = <0>;
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lvds0_in: endpoint {
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remote-endpoint = <&ipu_di0_lvds0>;
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};
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};
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port@2 {
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reg = <2>;
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};
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};
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lvds-channel@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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status = "disabled";
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port@1 {
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reg = <1>;
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lvds1_in: endpoint {
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remote-endpoint = <&ipu_di1_lvds1>;
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};
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};
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port@2 {
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reg = <2>;
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};
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};
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};
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};
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};
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