mirror of
https://github.com/brain-hackers/u-boot-brain
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98bcdf1635
Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
168 lines
3.5 KiB
C
168 lines
3.5 KiB
C
/*
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* Copyright 2018-2019 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mn_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/arch/ddr.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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struct udevice *dev;
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int ret;
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puts("Normal Boot\n");
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0)
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printf("Failed to find clock node. Check device tree\n");
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}
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#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("pca9450@25", &dev);
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if (ret == -ENODEV) {
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puts("No pca9450@25\n");
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return 0;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
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/* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
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#else
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/* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
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#endif
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/* Set DVS1 to 0.85v for suspend */
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/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
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pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
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/* set VDD_SNVS_0V8 from default 0.85V */
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pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
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/* enable LDO4 to 1.2v */
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pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44);
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/* set WDOG_B_CFG to cold reset */
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pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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enable_tzc380();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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