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https://github.com/brain-hackers/u-boot-brain
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b75d8dc564
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
83 lines
1.7 KiB
C
83 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* Common functions for OMAP4/5 based boards
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Without LPAE short descriptors are used
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* Set C - Cache Bit3
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* Set B - Buffer Bit2
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* The last 2 bits set to 0b10
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* Do Not set XN bit4
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* So value is 0xe
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*
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* With LPAE cache configuration happens via MAIR0 register
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* AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
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* 0xFF maps to Cache writeback with Read and Write Allocate set
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* The bits[1:0] should have the value 0b01 for the first level
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* descriptor.
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* So the value is 0xd
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*/
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#ifdef CONFIG_ARMV7_LPAE
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#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
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#else
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#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
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#endif
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#define ARMV7_DOMAIN_CLIENT 1
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#define ARMV7_DOMAIN_MASK (0x3 << 0)
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void enable_caches(void)
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{
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/* Enable I cache if not enabled */
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if (!icache_status())
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icache_enable();
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dcache_enable();
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}
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void dram_bank_mmu_setup(int bank)
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{
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struct bd_info *bd = gd->bd;
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int i;
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u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
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u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
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u32 end = start + size;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = start; i < end; i++)
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set_section_dcache(i, ARMV7_DCACHE_POLICY);
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}
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void arm_init_domains(void)
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{
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u32 reg;
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reg = get_dacr();
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/*
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* Set DOMAIN to client access so that all permissions
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* set in pagetables are validated by the mmu.
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*/
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reg &= ~ARMV7_DOMAIN_MASK;
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reg |= ARMV7_DOMAIN_CLIENT;
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set_dacr(reg);
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}
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