mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-24 19:08:50 +09:00
![Bin Meng](/assets/img/avatar_default.png)
U-Boot sets up the real mode interrupt handler stubs starting from address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff) system memory is reported as system RAM in E820 table to the OS. (see install_e820_map() implementation for each platform). So OS can use these memories whatever it wants. If U-Boot is in an S3 resume path, care must be taken not to corrupt these memorie otherwise OS data gets lost. Testing shows that, on Microsoft Windows 10 on Intel Baytrail its wake up vector happens to be installed at the same address 0x1000. While on Linux its wake up vector does not overlap this memory range, but after resume kernel checks low memory range per config option CONFIG_X86_RESERVE_LOW which is 64K by default to see whether a memory corruption occurs during the suspend/resume (it's harmless, but warnings are shown in the kernel dmesg logs). We cannot simply mark the these memory as reserved in E820 table because such configuration makes GRUB complain: unable to allocate real mode page. Hence we choose to back up these memories to the place where we reserved on our stack for our S3 resume work. Before jumping to OS wake up vector, we need restore the original content there. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Stefan Roese <sr@denx.de>
296 lines
5.7 KiB
C
296 lines
5.7 KiB
C
/*
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* (C) Copyright 2008-2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* Part of this file is adapted from coreboot
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* src/arch/x86/lib/cpu.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <syscon.h>
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#include <asm/acpi_s3.h>
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#include <asm/acpi_table.h>
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#include <asm/control_regs.h>
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#include <asm/coreboot_tables.h>
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#include <asm/cpu.h>
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#include <asm/lapic.h>
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#include <asm/microcode.h>
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#include <asm/mp.h>
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#include <asm/mrccache.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/interrupt.h>
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#include <asm/tables.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const char *const x86_vendor_name[] = {
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[X86_VENDOR_INTEL] = "Intel",
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[X86_VENDOR_CYRIX] = "Cyrix",
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[X86_VENDOR_AMD] = "AMD",
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[X86_VENDOR_UMC] = "UMC",
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[X86_VENDOR_NEXGEN] = "NexGen",
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[X86_VENDOR_CENTAUR] = "Centaur",
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[X86_VENDOR_RISE] = "Rise",
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[X86_VENDOR_TRANSMETA] = "Transmeta",
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[X86_VENDOR_NSC] = "NSC",
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[X86_VENDOR_SIS] = "SiS",
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};
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int __weak x86_cleanup_before_linux(void)
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{
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#ifdef CONFIG_BOOTSTAGE_STASH
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bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
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CONFIG_BOOTSTAGE_STASH_SIZE);
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#endif
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return 0;
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}
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int x86_init_cache(void)
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{
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enable_caches();
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return 0;
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}
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int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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printf("resetting ...\n");
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/* wait 50 ms */
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udelay(50000);
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disable_interrupts();
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reset_cpu(0);
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/*NOTREACHED*/
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return 0;
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}
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void flush_cache(unsigned long dummy1, unsigned long dummy2)
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{
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asm("wbinvd\n");
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}
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__weak void reset_cpu(ulong addr)
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{
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/* Do a hard reset through the chipset's reset control register */
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outb(SYS_RST | RST_CPU, IO_PORT_RESET);
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for (;;)
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cpu_hlt();
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}
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void x86_full_reset(void)
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{
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outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
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}
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/* Define these functions to allow ehch-hcd to function */
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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}
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void dcache_enable(void)
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{
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enable_caches();
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}
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void dcache_disable(void)
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{
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disable_caches();
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}
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 1;
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}
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const char *cpu_vendor_name(int vendor)
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{
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const char *name;
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name = "<invalid cpu vendor>";
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if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
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(x86_vendor_name[vendor] != 0))
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name = x86_vendor_name[vendor];
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return name;
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}
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char *cpu_get_name(char *name)
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{
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unsigned int *name_as_ints = (unsigned int *)name;
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struct cpuid_result regs;
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char *ptr;
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int i;
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/* This bit adds up to 48 bytes */
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for (i = 0; i < 3; i++) {
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regs = cpuid(0x80000002 + i);
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name_as_ints[i * 4 + 0] = regs.eax;
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name_as_ints[i * 4 + 1] = regs.ebx;
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name_as_ints[i * 4 + 2] = regs.ecx;
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name_as_ints[i * 4 + 3] = regs.edx;
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}
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name[CPU_MAX_NAME_LEN - 1] = '\0';
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/* Skip leading spaces. */
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ptr = name;
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while (*ptr == ' ')
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ptr++;
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return ptr;
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}
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int default_print_cpuinfo(void)
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{
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printf("CPU: %s, vendor %s, device %xh\n",
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cpu_has_64bit() ? "x86_64" : "x86",
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cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
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#ifdef CONFIG_HAVE_ACPI_RESUME
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debug("ACPI previous sleep state: %s\n",
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acpi_ss_string(gd->arch.prev_sleep_state));
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#endif
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return 0;
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}
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void show_boot_progress(int val)
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{
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outb(val, POST_PORT);
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}
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#ifndef CONFIG_SYS_COREBOOT
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/*
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* Implement a weak default function for boards that optionally
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* need to clean up the system before jumping to the kernel.
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*/
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__weak void board_final_cleanup(void)
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{
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}
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int last_stage_init(void)
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{
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board_final_cleanup();
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#if CONFIG_HAVE_ACPI_RESUME
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struct acpi_fadt *fadt = acpi_find_fadt();
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if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3)
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acpi_resume(fadt);
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#endif
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write_tables();
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return 0;
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}
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#endif
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static int x86_init_cpus(void)
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{
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#ifdef CONFIG_SMP
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debug("Init additional CPUs\n");
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x86_mp_init();
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#else
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struct udevice *dev;
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/*
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* This causes the cpu-x86 driver to be probed.
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* We don't check return value here as we want to allow boards
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* which have not been converted to use cpu uclass driver to boot.
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*/
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uclass_first_device(UCLASS_CPU, &dev);
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#endif
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return 0;
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}
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int cpu_init_r(void)
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{
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struct udevice *dev;
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int ret;
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if (!ll_boot_init())
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return 0;
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ret = x86_init_cpus();
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if (ret)
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return ret;
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/*
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* Set up the northbridge, PCH and LPC if available. Note that these
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* may have had some limited pre-relocation init if they were probed
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* before relocation, but this is post relocation.
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*/
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uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
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uclass_first_device(UCLASS_PCH, &dev);
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uclass_first_device(UCLASS_LPC, &dev);
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/* Set up pin control if available */
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ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
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debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
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return 0;
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}
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#ifndef CONFIG_EFI_STUB
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int reserve_arch(void)
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{
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#ifdef CONFIG_ENABLE_MRC_CACHE
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mrccache_reserve();
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#endif
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#ifdef CONFIG_SEABIOS
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high_table_reserve();
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#endif
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#ifdef CONFIG_HAVE_ACPI_RESUME
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acpi_s3_reserve();
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#ifdef CONFIG_HAVE_FSP
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/*
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* Save stack address to CMOS so that at next S3 boot,
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* we can use it as the stack address for fsp_contiue()
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*/
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fsp_save_s3_stack();
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#endif /* CONFIG_HAVE_FSP */
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#endif /* CONFIG_HAVE_ACPI_RESUME */
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return 0;
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}
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#endif
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