mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1dff14c87d
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
570 lines
12 KiB
ArmAsm
570 lines
12 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014-2015 Freescale Semiconductor
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* Copyright 2019 NXP
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*
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* Extracted from armv8/start.S
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/gic.h>
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#include <asm/macro.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#ifdef CONFIG_MP
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#include <asm/arch/mp.h>
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#endif
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#ifdef CONFIG_FSL_LSCH3
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#include <asm/arch-fsl-layerscape/immap_lsch3.h>
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#endif
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#include <asm/u-boot.h>
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/* Get GIC offset
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* For LS1043a rev1.0, GIC base address align with 4k.
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* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
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* is set, GIC base address align with 4K, or else align
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* with 64k.
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* output:
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* x0: the base address of GICD
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* x1: the base address of GICC
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*/
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ENTRY(get_gic_offset)
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ldr x0, =GICD_BASE
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#ifdef CONFIG_GICV2
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ldr x1, =GICC_BASE
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#endif
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#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
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ldr x2, =DCFG_CCSR_SVR
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ldr w2, [x2]
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rev w2, w2
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lsr w3, w2, #16
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ldr w4, =SVR_DEV(SVR_LS1043A)
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cmp w3, w4
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b.ne 1f
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ands w2, w2, #0xff
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cmp w2, #REV1_0
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b.eq 1f
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ldr x2, =SCFG_GIC400_ALIGN
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ldr w2, [x2]
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rev w2, w2
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tbnz w2, #GIC_ADDR_BIT, 1f
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ldr x0, =GICD_BASE_64K
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#ifdef CONFIG_GICV2
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ldr x1, =GICC_BASE_64K
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#endif
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1:
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#endif
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ret
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ENDPROC(get_gic_offset)
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ENTRY(smp_kick_all_cpus)
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/* Kick secondary cpus up by SGI 0 interrupt */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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mov x29, lr /* Save LR */
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bl get_gic_offset
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bl gic_kick_secondary_cpus
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mov lr, x29 /* Restore LR */
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#endif
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ret
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ENDPROC(smp_kick_all_cpus)
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ENTRY(lowlevel_init)
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mov x29, lr /* Save LR */
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/* unmask SError and abort */
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msr daifclr, #4
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/* Set HCR_EL2[AMO] so SError @EL2 is taken */
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mrs x0, hcr_el2
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orr x0, x0, #0x20 /* AMO */
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msr hcr_el2, x0
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isb
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switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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1:
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#if defined (CONFIG_SYS_FSL_HAS_CCN504)
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/* Set Wuo bit for RN-I 20 */
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#ifdef CONFIG_ARCH_LS2080A
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ldr x0, =CCI_AUX_CONTROL_BASE(20)
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ldr x1, =0x00000010
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bl ccn504_set_aux
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/*
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* Set forced-order mode in RNI-6, RNI-20
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* This is required for performance optimization on LS2088A
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* LS2080A family does not support setting forced-order mode,
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* so skip this operation for LS2080A family
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*/
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bl get_svr
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lsr w0, w0, #16
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ldr w1, =SVR_DEV(SVR_LS2080A)
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cmp w0, w1
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b.eq 1f
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ldr x0, =CCI_AUX_CONTROL_BASE(6)
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ldr x1, =0x00000020
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bl ccn504_set_aux
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ldr x0, =CCI_AUX_CONTROL_BASE(20)
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ldr x1, =0x00000020
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bl ccn504_set_aux
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1:
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#endif
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/* Add fully-coherent masters to DVM domain */
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ldr x0, =CCI_MN_BASE
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ldr x1, =CCI_MN_RNF_NODEID_LIST
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ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
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bl ccn504_add_masters_to_dvm
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/* Set all RN-I ports to QoS of 15 */
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
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#ifdef SMMU_BASE
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/* Set the SMMU page size in the sACR register */
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ldr x1, =SMMU_BASE
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ldr w0, [x1, #0x10]
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orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
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str w0, [x1, #0x10]
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#endif
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/* Initialize GIC Secure Bank Status */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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bl get_gic_offset
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bl gic_init_secure
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1:
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#ifdef CONFIG_GICV3
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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bl get_gic_offset
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bl gic_init_secure_percpu
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#endif
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#endif
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100:
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branch_if_master x0, x1, 2f
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#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
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ldr x0, =secondary_boot_func
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blr x0
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#endif
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2:
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switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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1:
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#ifdef CONFIG_FSL_TZPC_BP147
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/* Set Non Secure access for all devices protected via TZPC */
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ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
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orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
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str w0, [x1]
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isb
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dsb sy
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#endif
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#ifdef CONFIG_FSL_TZASC_400
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/*
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* LS2080 and its personalities does not support TZASC
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* So skip TZASC related operations
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*/
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bl get_svr
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lsr w0, w0, #16
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ldr w1, =SVR_DEV(SVR_LS2080A)
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cmp w0, w1
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b.eq 1f
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/* Set TZASC so that:
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* a. We use only Region0 whose global secure write/read is EN
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* b. We use only Region0 whose NSAID write/read is EN
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*
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* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
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* placeholders.
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*/
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.macro tzasc_prog, xreg
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mov x12, TZASC1_BASE
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mov x16, #0x10000
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mul x14, \xreg, x16
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add x14, x14,x12
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mov x1, #0x8
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add x1, x1, x14
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ldr w0, [x1] /* Filter 0 Gate Keeper Register */
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orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
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str w0, [x1]
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mov x1, #0x110
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add x1, x1, x14
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ldr w0, [x1] /* Region-0 Attributes Register */
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orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str w0, [x1]
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mov x1, #0x114
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add x1, x1, x14
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ldr w0, [x1] /* Region-0 Access Register */
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mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
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str w0, [x1]
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.endm
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#ifdef CONFIG_FSL_TZASC_1
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mov x13, #0
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tzasc_prog x13
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#endif
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#ifdef CONFIG_FSL_TZASC_2
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mov x13, #1
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tzasc_prog x13
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#endif
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isb
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dsb sy
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#endif
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100:
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1:
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#ifdef CONFIG_ARCH_LS1046A
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switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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1:
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/* Initialize the L2 RAM latency */
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mrs x1, S3_1_c11_c0_2
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mov x0, #0x1C7
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/* Clear L2 Tag RAM latency and L2 Data RAM latency */
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bic x1, x1, x0
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/* Set L2 data ram latency bits [2:0] */
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orr x1, x1, #0x2
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/* set L2 tag ram latency bits [8:6] */
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orr x1, x1, #0x80
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msr S3_1_c11_c0_2, x1
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isb
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100:
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#endif
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#if !defined(CONFIG_TFABOOT) && \
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(defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
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bl fsl_ocram_init
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#endif
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
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ENTRY(fsl_ocram_init)
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mov x28, lr /* Save LR */
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bl fsl_clear_ocram
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bl fsl_ocram_clear_ecc_err
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mov lr, x28 /* Restore LR */
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ret
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ENDPROC(fsl_ocram_init)
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ENTRY(fsl_clear_ocram)
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/* Clear OCRAM */
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ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
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ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
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mov x2, #0
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clear_loop:
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str x2, [x0]
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add x0, x0, #8
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cmp x0, x1
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b.lo clear_loop
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ret
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ENDPROC(fsl_clear_ocram)
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ENTRY(fsl_ocram_clear_ecc_err)
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/* OCRAM1/2 ECC status bit */
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mov w1, #0x60
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ldr x0, =DCSR_DCFG_SBEESR2
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str w1, [x0]
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ldr x0, =DCSR_DCFG_MBEESR2
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str w1, [x0]
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ret
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ENDPROC(fsl_ocram_init)
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#endif
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#ifdef CONFIG_FSL_LSCH3
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.globl get_svr
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get_svr:
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ldr x1, =FSL_LSCH3_SVR
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ldr w0, [x1]
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ret
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#endif
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#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
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hnf_pstate_poll:
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/* x0 has the desired status, return only if operation succeed
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* clobber x1, x2, x6
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*/
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mov x1, x0
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mov w6, #8 /* HN-F node count */
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mov x0, #0x18
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movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
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1:
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ldr x2, [x0]
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cmp x2, x1 /* check status */
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b.eq 2f
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b 1b
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2:
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add x0, x0, #0x10000 /* move to next node */
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subs w6, w6, #1
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cbnz w6, 1b
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ret
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hnf_set_pstate:
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/* x0 has the desired state, clobber x1, x2, x6 */
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mov x1, x0
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/* power state to SFONLY */
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mov w6, #8 /* HN-F node count */
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mov x0, #0x10
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movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
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1: /* set pstate to sfonly */
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ldr x2, [x0]
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and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
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orr x2, x2, x1
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str x2, [x0]
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add x0, x0, #0x10000 /* move to next node */
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subs w6, w6, #1
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cbnz w6, 1b
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ret
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ENTRY(__asm_flush_l3_dcache)
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/*
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* Return status in x0
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* success 0
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*/
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mov x29, lr
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dsb sy
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mov x0, #0x1 /* HNFPSTAT_SFONLY */
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bl hnf_set_pstate
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mov x0, #0x4 /* SFONLY status */
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bl hnf_pstate_poll
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dsb sy
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mov x0, #0x3 /* HNFPSTAT_FAM */
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bl hnf_set_pstate
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mov x0, #0xc /* FAM status */
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bl hnf_pstate_poll
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mov x0, #0
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mov lr, x29
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ret
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ENDPROC(__asm_flush_l3_dcache)
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#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
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#ifdef CONFIG_MP
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/* Keep literals not used by the secondary boot code outside it */
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.ltorg
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/* Using 64 bit alignment since the spin table is accessed as data */
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.align 4
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.global secondary_boot_code
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/* Secondary Boot Code starts here */
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secondary_boot_code:
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.global __spin_table
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__spin_table:
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.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
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.align 2
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ENTRY(secondary_boot_func)
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/*
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* MPIDR_EL1 Fields:
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* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
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* MPIDR[7:2] = AFF0_RES
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* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
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* MPIDR[23:16] = AFF2_CLUSTERID
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* MPIDR[24] = MT
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* MPIDR[29:25] = RES0
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* MPIDR[30] = U
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* MPIDR[31] = ME
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* MPIDR[39:32] = AFF3
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*
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* Linear Processor ID (LPID) calculation from MPIDR_EL1:
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* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
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* until AFF2_CLUSTERID and AFF3 have non-zero values)
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*
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* LPID = MPIDR[15:8] | MPIDR[1:0]
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*/
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
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/*
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* offset of the spin table element for this core from start of spin
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|
* table (each elem is padded to 64 bytes)
|
|
*/
|
|
lsl x1, x10, #6
|
|
ldr x0, =__spin_table
|
|
/* physical address of this cpus spin table element */
|
|
add x11, x1, x0
|
|
|
|
ldr x0, =__real_cntfrq
|
|
ldr x0, [x0]
|
|
msr cntfrq_el0, x0 /* set with real frequency */
|
|
str x9, [x11, #16] /* LPID */
|
|
mov x4, #1
|
|
str x4, [x11, #8] /* STATUS */
|
|
dsb sy
|
|
#if defined(CONFIG_GICV3)
|
|
gic_wait_for_interrupt_m x0
|
|
#elif defined(CONFIG_GICV2)
|
|
bl get_gic_offset
|
|
mov x0, x1
|
|
gic_wait_for_interrupt_m x0, w1
|
|
#endif
|
|
|
|
slave_cpu:
|
|
wfe
|
|
ldr x0, [x11]
|
|
cbz x0, slave_cpu
|
|
#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
|
|
mrs x1, sctlr_el2
|
|
#else
|
|
mrs x1, sctlr_el1
|
|
#endif
|
|
tbz x1, #25, cpu_is_le
|
|
rev x0, x0 /* BE to LE conversion */
|
|
cpu_is_le:
|
|
ldr x5, [x11, #24]
|
|
cbz x5, 1f
|
|
|
|
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
|
adr x4, secondary_switch_to_el1
|
|
ldr x5, =ES_TO_AARCH64
|
|
#else
|
|
ldr x4, [x11]
|
|
ldr x5, =ES_TO_AARCH32
|
|
#endif
|
|
bl secondary_switch_to_el2
|
|
|
|
1:
|
|
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
|
|
adr x4, secondary_switch_to_el1
|
|
#else
|
|
ldr x4, [x11]
|
|
#endif
|
|
ldr x5, =ES_TO_AARCH64
|
|
bl secondary_switch_to_el2
|
|
|
|
ENDPROC(secondary_boot_func)
|
|
|
|
ENTRY(secondary_switch_to_el2)
|
|
switch_el x6, 1f, 0f, 0f
|
|
0: ret
|
|
1: armv8_switch_to_el2_m x4, x5, x6
|
|
ENDPROC(secondary_switch_to_el2)
|
|
|
|
ENTRY(secondary_switch_to_el1)
|
|
mrs x0, mpidr_el1
|
|
ubfm x1, x0, #8, #15
|
|
ubfm x2, x0, #0, #1
|
|
orr x10, x2, x1, lsl #2 /* x10 has LPID */
|
|
|
|
lsl x1, x10, #6
|
|
ldr x0, =__spin_table
|
|
/* physical address of this cpus spin table element */
|
|
add x11, x1, x0
|
|
|
|
ldr x4, [x11]
|
|
|
|
ldr x5, [x11, #24]
|
|
cbz x5, 2f
|
|
|
|
ldr x5, =ES_TO_AARCH32
|
|
bl switch_to_el1
|
|
|
|
2: ldr x5, =ES_TO_AARCH64
|
|
|
|
switch_to_el1:
|
|
switch_el x6, 0f, 1f, 0f
|
|
0: ret
|
|
1: armv8_switch_to_el1_m x4, x5, x6
|
|
ENDPROC(secondary_switch_to_el1)
|
|
|
|
/* Ensure that the literals used by the secondary boot code are
|
|
* assembled within it (this is required so that we can protect
|
|
* this area with a single memreserve region
|
|
*/
|
|
.ltorg
|
|
|
|
/* 64 bit alignment for elements accessed as data */
|
|
.align 4
|
|
.global __real_cntfrq
|
|
__real_cntfrq:
|
|
.quad COUNTER_FREQUENCY
|
|
.globl __secondary_boot_code_size
|
|
.type __secondary_boot_code_size, %object
|
|
/* Secondary Boot Code ends here */
|
|
__secondary_boot_code_size:
|
|
.quad .-secondary_boot_code
|
|
#endif
|