mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-18 10:44:13 +09:00
d5dae85f23
Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
/*
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* Copyright (c) 2013 Xilinx Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
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#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
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#define ZYNQ_SCU_BASEADDR 0xF8F00000
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#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
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#define ZYNQ_GEM_BASEADDR0 0xE000B000
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#define ZYNQ_GEM_BASEADDR1 0xE000C000
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#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
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#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
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#define ZYNQ_I2C_BASEADDR0 0xE0004000
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#define ZYNQ_I2C_BASEADDR1 0xE0005000
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/* Reflect slcr offsets */
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struct slcr_regs {
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u32 scl; /* 0x0 */
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u32 slcr_lock; /* 0x4 */
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u32 slcr_unlock; /* 0x8 */
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u32 reserved0[75];
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u32 gem0_rclk_ctrl; /* 0x138 */
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u32 gem1_rclk_ctrl; /* 0x13c */
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u32 gem0_clk_ctrl; /* 0x140 */
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u32 gem1_clk_ctrl; /* 0x144 */
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u32 reserved1[46];
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u32 pss_rst_ctrl; /* 0x200 */
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u32 reserved2[15];
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u32 fpga_rst_ctrl; /* 0x240 */
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u32 reserved3[5];
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u32 reboot_status; /* 0x258 */
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u32 boot_mode; /* 0x25c */
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u32 reserved4[116];
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u32 trust_zone; /* 0x430 */ /* FIXME */
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u32 reserved5_1[63];
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u32 pss_idcode; /* 0x530 */
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u32 reserved5_2[51];
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u32 ddr_urgent; /* 0x600 */
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u32 reserved6[6];
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u32 ddr_urgent_sel; /* 0x61c */
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u32 reserved7[56];
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u32 mio_pin[54]; /* 0x700 - 0x7D4 */
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u32 reserved8[74];
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u32 lvl_shftr_en; /* 0x900 */
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u32 reserved9[3];
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u32 ocm_cfg; /* 0x910 */
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};
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#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
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struct devcfg_regs {
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u32 ctrl; /* 0x0 */
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u32 lock; /* 0x4 */
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u32 cfg; /* 0x8 */
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u32 int_sts; /* 0xc */
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u32 int_mask; /* 0x10 */
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u32 status; /* 0x14 */
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u32 dma_src_addr; /* 0x18 */
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u32 dma_dst_addr; /* 0x1c */
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u32 dma_src_len; /* 0x20 */
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u32 dma_dst_len; /* 0x24 */
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u32 rom_shadow; /* 0x28 */
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u32 reserved1[2];
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u32 unlock; /* 0x34 */
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u32 reserved2[18];
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u32 mctrl; /* 0x80 */
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u32 reserved3;
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u32 write_count; /* 0x88 */
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u32 read_count; /* 0x8c */
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};
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#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
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struct scu_regs {
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u32 reserved1[16];
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u32 filter_start; /* 0x40 */
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u32 filter_end; /* 0x44 */
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};
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#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
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#endif /* _ASM_ARCH_HARDWARE_H */
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