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https://github.com/brain-hackers/u-boot-brain
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![York Sun](/assets/img/avatar_default.png)
When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com>
534 lines
12 KiB
C
534 lines
12 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ifc.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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#include <asm/arch-fsl-layerscape/config.h>
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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#include <fsl_csu.h>
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#endif
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#ifdef CONFIG_SYS_FSL_DDR
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr.h>
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#endif
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#ifdef CONFIG_CHAIN_OF_TRUST
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#include <fsl_validate.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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bool soc_has_dp_ddr(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 svr = gur_in32(&gur->svr);
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/* LS2085A, LS2088A, LS2048A has DP_DDR */
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if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
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(SVR_SOC_VER(svr) == SVR_LS2088A) ||
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(SVR_SOC_VER(svr) == SVR_LS2048A))
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return true;
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return false;
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}
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bool soc_has_aiop(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 svr = gur_in32(&gur->svr);
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/* LS2085A has AIOP */
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if (SVR_SOC_VER(svr) == SVR_LS2085A)
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return true;
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return false;
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}
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#if defined(CONFIG_FSL_LSCH3)
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/*
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* This erratum requires setting a value to eddrtqcr1 to
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* optimal the DDR performance.
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*/
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static void erratum_a008336(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
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u32 *eddrtqcr1;
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#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
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if (fsl_ddr_get_version(0) == 0x50200)
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out_le32(eddrtqcr1, 0x63b30002);
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#endif
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#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
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if (fsl_ddr_get_version(0) == 0x50200)
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out_le32(eddrtqcr1, 0x63b30002);
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#endif
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#endif
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}
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/*
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* This erratum requires a register write before being Memory
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* controller 3 being enabled.
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*/
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static void erratum_a008514(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
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u32 *eddrtqcr1;
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#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
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out_le32(eddrtqcr1, 0x63b20002);
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#endif
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#endif
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
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static unsigned long get_internval_val_mhz(void)
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{
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char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
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/*
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* interval is the number of platform cycles(MHz) between
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* wake up events generated by EPU.
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*/
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ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
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if (interval)
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interval_mhz = simple_strtoul(interval, NULL, 10);
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return interval_mhz;
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}
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void erratum_a009635(void)
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{
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u32 val;
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unsigned long interval_mhz = get_internval_val_mhz();
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if (!interval_mhz)
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return;
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val = in_le32(DCSR_CGACRE5);
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writel(val | 0x00000200, DCSR_CGACRE5);
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val = in_le32(EPU_EPCMPR5);
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writel(interval_mhz, EPU_EPCMPR5);
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val = in_le32(EPU_EPCCR5);
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writel(val | 0x82820000, EPU_EPCCR5);
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val = in_le32(EPU_EPSMCR5);
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writel(val | 0x002f0000, EPU_EPSMCR5);
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val = in_le32(EPU_EPECR5);
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writel(val | 0x20000000, EPU_EPECR5);
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val = in_le32(EPU_EPGCR);
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writel(val | 0x80000000, EPU_EPGCR);
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}
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
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static void erratum_rcw_src(void)
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{
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#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
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u32 val;
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val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
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val &= ~DCFG_PORSR1_RCW_SRC;
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val |= DCFG_PORSR1_RCW_SRC_NOR;
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out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
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#endif
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}
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#define I2C_DEBUG_REG 0x6
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#define I2C_GLITCH_EN 0x8
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/*
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* This erratum requires setting glitch_en bit to enable
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* digital glitch filter to improve clock stability.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
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static void erratum_a009203(void)
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{
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u8 __iomem *ptr;
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#ifdef CONFIG_SYS_I2C
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#ifdef I2C1_BASE_ADDR
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ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C2_BASE_ADDR
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ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C3_BASE_ADDR
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ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C4_BASE_ADDR
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ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#endif
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}
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#endif
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void bypass_smmu(void)
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{
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u32 val;
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val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_SCR0, val);
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val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_NSCR0, val);
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}
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void fsl_lsch3_early_init_f(void)
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{
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erratum_rcw_src();
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init_early_memctl_regs(); /* tighten IFC timing */
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
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erratum_a009203();
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#endif
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erratum_a008514();
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erratum_a008336();
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#ifdef CONFIG_CHAIN_OF_TRUST
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/* In case of Secure Boot, the IBR configures the SMMU
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* to allow only Secure transactions.
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* SMMU must be reset in bypass mode.
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* Set the ClientPD bit and Clear the USFCFG Bit
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*/
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if (fsl_check_boot_mode_secure() == 1)
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bypass_smmu();
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#endif
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}
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#ifdef CONFIG_SCSI_AHCI_PLAT
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int sata_init(void)
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{
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struct ccsr_ahci __iomem *ccsr_ahci;
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ccsr_ahci = (void *)CONFIG_SYS_SATA2;
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
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ccsr_ahci = (void *)CONFIG_SYS_SATA1;
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
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ahci_init((void __iomem *)CONFIG_SYS_SATA1);
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scsi_scan(0);
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return 0;
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}
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#endif
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#elif defined(CONFIG_FSL_LSCH2)
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#ifdef CONFIG_SCSI_AHCI_PLAT
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int sata_init(void)
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{
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struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
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/* Disable SATA ECC */
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out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
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out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
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ahci_init((void __iomem *)CONFIG_SYS_SATA);
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scsi_scan(0);
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return 0;
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}
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#endif
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static void erratum_a009929(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
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struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
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u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
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rstrqmr1 |= 0x00000400;
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gur_out32(&gur->rstrqmr1, rstrqmr1);
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writel(0x01000000, dcsr_cop_ccp);
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#endif
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}
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/*
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* This erratum requires setting a value to eddrtqcr1 to optimal
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* the DDR performance. The eddrtqcr1 register is in SCFG space
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* of LS1043A and the offset is 0x157_020c.
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*/
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#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
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&& defined(CONFIG_SYS_FSL_ERRATUM_A008514)
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#error A009660 and A008514 can not be both enabled.
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#endif
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static void erratum_a009660(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
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u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
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out_be32(eddrtqcr1, 0x63b20042);
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#endif
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}
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static void erratum_a008850_early(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
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/* part 1 of 2 */
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struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
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struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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/* Skip if running at lower exception level */
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if (current_el() < 3)
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return;
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/* disables propagation of barrier transactions to DDRC from CCI400 */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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/* disable the re-ordering in DDRC */
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ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
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#endif
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}
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void erratum_a008850_post(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
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/* part 2 of 2 */
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struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
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struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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u32 tmp;
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/* Skip if running at lower exception level */
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if (current_el() < 3)
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return;
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/* enable propagation of barrier transactions to DDRC from CCI400 */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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/* enable the re-ordering in DDRC */
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tmp = ddr_in32(&ddr->eor);
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tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
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ddr_out32(&ddr->eor, tmp);
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#endif
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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void erratum_a010315(void)
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{
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int i;
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for (i = PCIE1; i <= PCIE4; i++)
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if (!is_serdes_configured(i)) {
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debug("PCIe%d: disabled all R/W permission!\n", i);
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set_pcie_ns_access(i, 0);
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}
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}
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#endif
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static void erratum_a010539(void)
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{
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#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 porsr1;
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porsr1 = in_be32(&gur->porsr1);
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porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
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out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
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porsr1);
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#endif
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}
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/* Get VDD in the unit mV from voltage ID */
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int get_core_volt_from_fuse(void)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int vdd;
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u32 fusesr;
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u8 vid;
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fusesr = in_be32(&gur->dcfg_fusesr);
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debug("%s: fusesr = 0x%x\n", __func__, fusesr);
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vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
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FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
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if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
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vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
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FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
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}
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debug("%s: VID = 0x%x\n", __func__, vid);
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switch (vid) {
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case 0x00: /* VID isn't supported */
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vdd = -EINVAL;
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debug("%s: The VID feature is not supported\n", __func__);
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break;
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case 0x08: /* 0.9V silicon */
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vdd = 900;
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break;
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case 0x10: /* 1.0V silicon */
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vdd = 1000;
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break;
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default: /* Other core voltage */
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vdd = -EINVAL;
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printf("%s: The VID(%x) isn't supported\n", __func__, vid);
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break;
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}
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debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
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return vdd;
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}
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__weak int board_switch_core_volt(u32 vdd)
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{
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return 0;
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}
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static int setup_core_volt(u32 vdd)
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{
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return board_setup_core_volt(vdd);
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}
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#ifdef CONFIG_SYS_FSL_DDR
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static void ddr_enable_0v9_volt(bool en)
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{
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struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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u32 tmp;
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tmp = ddr_in32(&ddr->ddr_cdr1);
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if (en)
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tmp |= DDR_CDR1_V0PT9_EN;
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else
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tmp &= ~DDR_CDR1_V0PT9_EN;
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ddr_out32(&ddr->ddr_cdr1, tmp);
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}
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#endif
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int setup_chip_volt(void)
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{
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int vdd;
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vdd = get_core_volt_from_fuse();
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/* Nothing to do for silicons doesn't support VID */
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if (vdd < 0)
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return vdd;
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if (setup_core_volt(vdd))
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printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
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#ifdef CONFIG_SYS_HAS_SERDES
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if (setup_serdes_volt(vdd))
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printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
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#endif
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#ifdef CONFIG_SYS_FSL_DDR
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if (vdd == 900)
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ddr_enable_0v9_volt(true);
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#endif
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return 0;
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}
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void fsl_lsch2_early_init_f(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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#ifdef CONFIG_FSL_IFC
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init_early_memctl_regs(); /* tighten IFC timing */
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#endif
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#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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/* Make SEC reads and writes snoopable */
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setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
|
|
SCFG_SNPCNFGCR_SECWRSNP |
|
|
SCFG_SNPCNFGCR_SATARDSNP |
|
|
SCFG_SNPCNFGCR_SATAWRSNP);
|
|
|
|
/*
|
|
* Enable snoop requests and DVM message requests for
|
|
* Slave insterface S4 (A53 core cluster)
|
|
*/
|
|
if (current_el() == 3) {
|
|
out_le32(&cci->slave[4].snoop_ctrl,
|
|
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
|
|
}
|
|
|
|
/* Erratum */
|
|
erratum_a008850_early(); /* part 1 of 2 */
|
|
erratum_a009929();
|
|
erratum_a009660();
|
|
erratum_a010539();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_QSPI_AHB_INIT
|
|
/* Enable 4bytes address support and fast read */
|
|
int qspi_ahb_init(void)
|
|
{
|
|
u32 *qspi_lut, lut_key, *qspi_key;
|
|
|
|
qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
|
|
qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
|
|
|
|
lut_key = in_be32(qspi_key);
|
|
|
|
if (lut_key == 0x5af05af0) {
|
|
/* That means the register is BE */
|
|
out_be32(qspi_key, 0x5af05af0);
|
|
/* Unlock the lut table */
|
|
out_be32(qspi_key + 1, 0x00000002);
|
|
out_be32(qspi_lut, 0x0820040c);
|
|
out_be32(qspi_lut + 1, 0x1c080c08);
|
|
out_be32(qspi_lut + 2, 0x00002400);
|
|
/* Lock the lut table */
|
|
out_be32(qspi_key, 0x5af05af0);
|
|
out_be32(qspi_key + 1, 0x00000001);
|
|
} else {
|
|
/* That means the register is LE */
|
|
out_le32(qspi_key, 0x5af05af0);
|
|
/* Unlock the lut table */
|
|
out_le32(qspi_key + 1, 0x00000002);
|
|
out_le32(qspi_lut, 0x0820040c);
|
|
out_le32(qspi_lut + 1, 0x1c080c08);
|
|
out_le32(qspi_lut + 2, 0x00002400);
|
|
/* Lock the lut table */
|
|
out_le32(qspi_key, 0x5af05af0);
|
|
out_le32(qspi_key + 1, 0x00000001);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_BOARD_LATE_INIT
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_SCSI_AHCI_PLAT
|
|
sata_init();
|
|
#endif
|
|
#ifdef CONFIG_CHAIN_OF_TRUST
|
|
fsl_setenv_chain_of_trust();
|
|
#endif
|
|
#ifdef CONFIG_QSPI_AHB_INIT
|
|
qspi_ahb_init();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif
|