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https://github.com/brain-hackers/u-boot-brain
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![Bogdan Purcareata](/assets/img/avatar_default.png)
When multiple PCI cards are present in an ls2080a board, the second card does not get its msi-map set up properly due to a bug in computing the bus number. The bus number returned by PCI_BDF() is not the actual PCI bus number, but instead represents a global u-boot PCI bus number. A given bus number is relative to hose->first_busno, so that has to be subtracted from the PCI device id. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Acked-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
817 lines
21 KiB
C
817 lines
21 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <malloc.h>
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#ifndef CONFIG_LS102XA
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#include <asm/arch/fdt.h>
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#include <asm/arch/soc.h>
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#endif
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#ifndef CONFIG_SYS_PCI_MEMORY_BUS
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#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
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#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
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#endif
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#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
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#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
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#endif
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#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
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#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
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#endif
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/* iATU registers */
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
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#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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#define PCIE_DBI_RO_WR_EN 0x8bc
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#define PCIE_LINK_CAP 0x7c
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#define PCIE_LINK_SPEED_MASK 0xf
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#define PCIE_LINK_STA 0x82
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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#define PCIE_DBI_SIZE 0x100000 /* 1M */
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#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
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#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
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#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
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#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
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#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
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PCIE_LCTRL0_VF(vf) | \
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((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
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PCIE_LCTRL0_CFG2_ENABLE)
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#define PCIE_NO_SRIOV_BAR_BASE 0x1000
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#define PCIE_PF_NUM 2
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#define PCIE_VF_NUM 64
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#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
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#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
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#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
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#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
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struct ls_pcie {
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int idx;
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void __iomem *dbi;
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void __iomem *va_cfg0;
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void __iomem *va_cfg1;
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int next_lut_index;
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struct pci_controller hose;
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};
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struct ls_pcie_info {
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unsigned long regs;
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int pci_num;
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u64 phys_base;
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u64 cfg0_phys;
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u64 cfg0_size;
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u64 cfg1_phys;
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u64 cfg1_size;
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u64 mem_bus;
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u64 mem_phys;
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u64 mem_size;
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u64 io_bus;
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u64 io_phys;
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u64 io_size;
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};
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#define SET_LS_PCIE_INFO(x, num) \
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{ \
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x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
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x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
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x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
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x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
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x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
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x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
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x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
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CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
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x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
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x.pci_num = num; \
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}
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#ifdef CONFIG_LS102XA
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#include <asm/arch/immap_ls102xa.h>
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/* PEX1/2 Misc Ports Status Register */
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#define LTSSM_STATE_SHIFT 20
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static int ls_pcie_link_state(struct ls_pcie *pcie)
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{
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u32 state;
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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state = in_be32(&scfg->pexmscportsr[pcie->idx]);
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state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0) {
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debug("....PCIe link error. LTSSM=0x%02x.\n", state);
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return 0;
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}
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return 1;
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}
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#else
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static int ls_pcie_link_state(struct ls_pcie *pcie)
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{
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u32 state;
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state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
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LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0) {
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debug("....PCIe link error. LTSSM=0x%02x.\n", state);
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return 0;
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}
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return 1;
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}
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#endif
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static int ls_pcie_link_up(struct ls_pcie *pcie)
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{
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int state;
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u32 cap;
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state = ls_pcie_link_state(pcie);
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if (state)
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return state;
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/* Try to download speed to gen1 */
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cap = readl(pcie->dbi + PCIE_LINK_CAP);
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writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
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/*
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* Notice: the following delay has critical impact on link training
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* if too short (<30ms) the link doesn't get up.
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*/
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mdelay(100);
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state = ls_pcie_link_state(pcie);
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if (state)
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return state;
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writel(cap, pcie->dbi + PCIE_LINK_CAP);
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return 0;
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}
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static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
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{
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writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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pcie->dbi + PCIE_ATU_VIEWPORT);
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writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
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{
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writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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pcie->dbi + PCIE_ATU_VIEWPORT);
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writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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}
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static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
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u64 phys, u64 bus_addr, pci_size_t size)
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{
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writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
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writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
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writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
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writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
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writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
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writel(type, pcie->dbi + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
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}
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/* Use bar match mode and MEM type as default */
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static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
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int bar, u64 phys)
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{
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writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
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writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
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writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
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writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
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writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
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PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
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}
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static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
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{
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#ifdef DEBUG
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int i;
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#endif
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/* ATU 0 : OUTBOUND : CFG0 */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_CFG0,
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info->cfg0_phys,
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0,
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info->cfg0_size);
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/* ATU 1 : OUTBOUND : CFG1 */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_CFG1,
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info->cfg1_phys,
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0,
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info->cfg1_size);
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/* ATU 2 : OUTBOUND : MEM */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
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PCIE_ATU_TYPE_MEM,
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info->mem_phys,
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info->mem_bus,
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info->mem_size);
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/* ATU 3 : OUTBOUND : IO */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
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PCIE_ATU_TYPE_IO,
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info->io_phys,
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info->io_bus,
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info->io_size);
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#ifdef DEBUG
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for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
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writel(PCIE_ATU_REGION_OUTBOUND | i,
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pcie->dbi + PCIE_ATU_VIEWPORT);
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debug("iATU%d:\n", i);
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debug("\tLOWER PHYS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
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debug("\tUPPER PHYS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
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debug("\tLOWER BUS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
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debug("\tUPPER BUS 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
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debug("\tLIMIT 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_LIMIT));
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debug("\tCR1 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_CR1));
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debug("\tCR2 0x%08x\n",
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readl(pcie->dbi + PCIE_ATU_CR2));
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}
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#endif
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}
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int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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/* Do not skip controller */
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return 0;
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}
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static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
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{
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if (PCI_DEV(d) > 0)
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return -EINVAL;
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/* Controller does not support multi-function in RC mode */
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if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
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return -EINVAL;
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return 0;
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}
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static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 *val)
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{
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struct ls_pcie *pcie = hose->priv_data;
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u32 busdev, *addr;
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if (ls_pcie_addr_valid(hose, d)) {
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*val = 0xffffffff;
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return 0;
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}
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if (PCI_BUS(d) == hose->first_busno) {
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addr = pcie->dbi + (where & ~0x3);
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} else {
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busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
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PCIE_ATU_DEV(PCI_DEV(d)) |
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PCIE_ATU_FUNC(PCI_FUNC(d));
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if (PCI_BUS(d) == hose->first_busno + 1) {
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ls_pcie_cfg0_set_busdev(pcie, busdev);
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addr = pcie->va_cfg0 + (where & ~0x3);
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} else {
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ls_pcie_cfg1_set_busdev(pcie, busdev);
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addr = pcie->va_cfg1 + (where & ~0x3);
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}
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}
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*val = readl(addr);
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return 0;
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}
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static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 val)
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{
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struct ls_pcie *pcie = hose->priv_data;
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u32 busdev, *addr;
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if (ls_pcie_addr_valid(hose, d))
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return -EINVAL;
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if (PCI_BUS(d) == hose->first_busno) {
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addr = pcie->dbi + (where & ~0x3);
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} else {
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busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
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PCIE_ATU_DEV(PCI_DEV(d)) |
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PCIE_ATU_FUNC(PCI_FUNC(d));
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if (PCI_BUS(d) == hose->first_busno + 1) {
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ls_pcie_cfg0_set_busdev(pcie, busdev);
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addr = pcie->va_cfg0 + (where & ~0x3);
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} else {
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ls_pcie_cfg1_set_busdev(pcie, busdev);
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addr = pcie->va_cfg1 + (where & ~0x3);
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}
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}
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writel(val, addr);
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return 0;
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}
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static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
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struct ls_pcie_info *info)
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{
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struct pci_controller *hose = &pcie->hose;
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pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
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ls_pcie_setup_atu(pcie, info);
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pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
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/* program correct class for RC */
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writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
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pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
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PCI_CLASS_BRIDGE_PCI);
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#ifndef CONFIG_LS102XA
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writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
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#endif
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}
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static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
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struct ls_pcie_info *info)
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{
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u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
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/* ATU 0 : INBOUND : map BAR0 */
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
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/* ATU 1 : INBOUND : map BAR1 */
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phys += PCIE_BAR1_SIZE;
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
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/* ATU 2 : INBOUND : map BAR2 */
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phys += PCIE_BAR2_SIZE;
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
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/* ATU 3 : INBOUND : map BAR4 */
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phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
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ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
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/* ATU 0 : OUTBOUND : map 4G MEM */
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ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM,
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info->phys_base,
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0,
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4 * 1024 * 1024 * 1024ULL);
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}
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/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
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static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
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{
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if (size < 4 * 1024)
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return;
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switch (bar) {
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case 0:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
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break;
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case 1:
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writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
|
|
break;
|
|
case 2:
|
|
writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
|
|
writel(0, bar_base + PCI_BASE_ADDRESS_3);
|
|
break;
|
|
case 4:
|
|
writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
|
|
writel(0, bar_base + PCI_BASE_ADDRESS_5);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ls_pcie_ep_setup_bars(void *bar_base)
|
|
{
|
|
/* BAR0 - 32bit - 4K configuration */
|
|
ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
|
|
/* BAR1 - 32bit - 8K MSIX*/
|
|
ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
|
|
/* BAR2 - 64bit - 4K MEM desciptor */
|
|
ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
|
|
/* BAR4 - 64bit - 1M MEM*/
|
|
ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
|
|
}
|
|
|
|
static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
|
|
{
|
|
struct pci_controller *hose = &pcie->hose;
|
|
pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
|
|
int sriov;
|
|
|
|
sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
|
|
if (sriov) {
|
|
int pf, vf;
|
|
|
|
for (pf = 0; pf < PCIE_PF_NUM; pf++) {
|
|
for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
|
|
#ifndef CONFIG_LS102XA
|
|
writel(PCIE_LCTRL0_VAL(pf, vf),
|
|
pcie->dbi + PCIE_LUT_BASE +
|
|
PCIE_LUT_LCTRL0);
|
|
#endif
|
|
ls_pcie_ep_setup_bars(pcie->dbi);
|
|
ls_pcie_ep_setup_atu(pcie, info);
|
|
}
|
|
}
|
|
|
|
/* Disable CFG2 */
|
|
#ifndef CONFIG_LS102XA
|
|
writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
|
|
#endif
|
|
} else {
|
|
ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
|
|
ls_pcie_ep_setup_atu(pcie, info);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_LSCH3
|
|
/*
|
|
* Return next available LUT index.
|
|
*/
|
|
static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
|
|
{
|
|
if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
|
|
return pcie->next_lut_index++;
|
|
else
|
|
return -1; /* LUT is full */
|
|
}
|
|
|
|
/*
|
|
* Program a single LUT entry
|
|
*/
|
|
static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
|
|
u32 streamid)
|
|
{
|
|
void __iomem *lut;
|
|
|
|
lut = pcie->dbi + PCIE_LUT_BASE;
|
|
|
|
/* leave mask as all zeroes, want to match all bits */
|
|
writel((devid << 16), lut + PCIE_LUT_UDR(index));
|
|
writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
|
|
}
|
|
|
|
/* returns the next available streamid */
|
|
static u32 ls_pcie_next_streamid(void)
|
|
{
|
|
static int next_stream_id = FSL_PEX_STREAM_ID_START;
|
|
|
|
if (next_stream_id > FSL_PEX_STREAM_ID_END)
|
|
return 0xffffffff;
|
|
|
|
return next_stream_id++;
|
|
}
|
|
|
|
/*
|
|
* An msi-map is a property to be added to the pci controller
|
|
* node. It is a table, where each entry consists of 4 fields
|
|
* e.g.:
|
|
*
|
|
* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
|
|
* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
|
|
*/
|
|
static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
|
|
u32 devid, u32 streamid)
|
|
{
|
|
char pcie_path[19];
|
|
u32 *prop;
|
|
u32 phandle;
|
|
int nodeoffset;
|
|
|
|
/* find pci controller node */
|
|
snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
|
|
(u64)pcie->dbi);
|
|
nodeoffset = fdt_path_offset(blob, pcie_path);
|
|
if (nodeoffset < 0) {
|
|
printf("\n%s: ERROR: unable to update PCIe node: %s\n",
|
|
__func__, pcie_path);
|
|
return;
|
|
}
|
|
|
|
/* get phandle to MSI controller */
|
|
prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
|
|
if (prop == NULL) {
|
|
printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
|
|
pcie_path);
|
|
return;
|
|
}
|
|
phandle = be32_to_cpu(*prop);
|
|
|
|
/* set one msi-map row */
|
|
fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
|
|
fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
|
|
fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
|
|
fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
|
|
}
|
|
|
|
static void fdt_fixup_pcie(void *blob)
|
|
{
|
|
unsigned int found_multi = 0;
|
|
unsigned char header_type;
|
|
int index;
|
|
u32 streamid;
|
|
pci_dev_t dev, bdf;
|
|
int bus;
|
|
unsigned short id;
|
|
struct pci_controller *hose;
|
|
struct ls_pcie *pcie;
|
|
int i;
|
|
|
|
for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
|
|
pcie = hose->priv_data;
|
|
for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
|
|
|
|
for (dev = PCI_BDF(bus, 0, 0);
|
|
dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
|
|
PCI_MAX_PCI_FUNCTIONS - 1);
|
|
dev += PCI_BDF(0, 0, 1)) {
|
|
|
|
if (PCI_FUNC(dev) && !found_multi)
|
|
continue;
|
|
|
|
pci_read_config_word(dev, PCI_VENDOR_ID, &id);
|
|
|
|
pci_read_config_byte(dev, PCI_HEADER_TYPE,
|
|
&header_type);
|
|
|
|
if ((id == 0xFFFF) || (id == 0x0000))
|
|
continue;
|
|
|
|
if (!PCI_FUNC(dev))
|
|
found_multi = header_type & 0x80;
|
|
|
|
streamid = ls_pcie_next_streamid();
|
|
if (streamid == 0xffffffff) {
|
|
printf("ERROR: no stream ids free\n");
|
|
continue;
|
|
}
|
|
|
|
index = ls_pcie_next_lut_index(pcie);
|
|
if (index < 0) {
|
|
printf("ERROR: no LUT indexes free\n");
|
|
continue;
|
|
}
|
|
|
|
/* the DT fixup must be relative to the hose first_busno */
|
|
bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
|
|
|
|
/* map PCI b.d.f to streamID in LUT */
|
|
ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
|
|
streamid);
|
|
|
|
/* update msi-map in device tree */
|
|
fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
|
|
streamid);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
|
|
{
|
|
struct ls_pcie *pcie;
|
|
struct pci_controller *hose;
|
|
int num = dev - PCIE1;
|
|
pci_dev_t pdev = PCI_BDF(busno, 0, 0);
|
|
int i, linkup, ep_mode;
|
|
u8 header_type;
|
|
u16 temp16;
|
|
|
|
if (!is_serdes_configured(dev)) {
|
|
printf("PCIe%d: disabled\n", num + 1);
|
|
return busno;
|
|
}
|
|
|
|
pcie = malloc(sizeof(*pcie));
|
|
if (!pcie)
|
|
return busno;
|
|
memset(pcie, 0, sizeof(*pcie));
|
|
|
|
hose = &pcie->hose;
|
|
hose->priv_data = pcie;
|
|
hose->first_busno = busno;
|
|
pcie->idx = num;
|
|
pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
|
|
pcie->va_cfg0 = map_physmem(info->cfg0_phys,
|
|
info->cfg0_size,
|
|
MAP_NOCACHE);
|
|
pcie->va_cfg1 = map_physmem(info->cfg1_phys,
|
|
info->cfg1_size,
|
|
MAP_NOCACHE);
|
|
pcie->next_lut_index = 0;
|
|
|
|
/* outbound memory */
|
|
pci_set_region(&hose->regions[0],
|
|
(pci_size_t)info->mem_bus,
|
|
(phys_size_t)info->mem_phys,
|
|
(pci_size_t)info->mem_size,
|
|
PCI_REGION_MEM);
|
|
|
|
/* outbound io */
|
|
pci_set_region(&hose->regions[1],
|
|
(pci_size_t)info->io_bus,
|
|
(phys_size_t)info->io_phys,
|
|
(pci_size_t)info->io_size,
|
|
PCI_REGION_IO);
|
|
|
|
/* System memory space */
|
|
pci_set_region(&hose->regions[2],
|
|
CONFIG_SYS_PCI_MEMORY_BUS,
|
|
CONFIG_SYS_PCI_MEMORY_PHYS,
|
|
CONFIG_SYS_PCI_MEMORY_SIZE,
|
|
PCI_REGION_SYS_MEMORY);
|
|
|
|
hose->region_count = 3;
|
|
|
|
for (i = 0; i < hose->region_count; i++)
|
|
debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
|
|
i,
|
|
(u64)hose->regions[i].phys_start,
|
|
(u64)hose->regions[i].bus_start,
|
|
(u64)hose->regions[i].size,
|
|
hose->regions[i].flags);
|
|
|
|
pci_set_ops(hose,
|
|
pci_hose_read_config_byte_via_dword,
|
|
pci_hose_read_config_word_via_dword,
|
|
ls_pcie_read_config,
|
|
pci_hose_write_config_byte_via_dword,
|
|
pci_hose_write_config_word_via_dword,
|
|
ls_pcie_write_config);
|
|
|
|
pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
|
|
ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
|
|
printf("PCIe%u: %s ", info->pci_num,
|
|
ep_mode ? "Endpoint" : "Root Complex");
|
|
|
|
if (ep_mode)
|
|
ls_pcie_setup_ep(pcie, info);
|
|
else
|
|
ls_pcie_setup_ctrl(pcie, info);
|
|
|
|
linkup = ls_pcie_link_up(pcie);
|
|
|
|
if (!linkup) {
|
|
/* Let the user know there's no PCIe link */
|
|
printf("no link, regs @ 0x%lx\n", info->regs);
|
|
hose->last_busno = hose->first_busno;
|
|
return busno;
|
|
}
|
|
|
|
/* Print the negotiated PCIe link width */
|
|
pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
|
|
printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
|
|
(temp16 & 0xf), info->regs);
|
|
|
|
if (ep_mode)
|
|
return busno;
|
|
|
|
pci_register_hose(hose);
|
|
|
|
hose->last_busno = pci_hose_scan(hose);
|
|
|
|
printf("PCIe%x: Bus %02x - %02x\n",
|
|
info->pci_num, hose->first_busno, hose->last_busno);
|
|
|
|
return hose->last_busno + 1;
|
|
}
|
|
|
|
int ls_pcie_init_board(int busno)
|
|
{
|
|
struct ls_pcie_info info;
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
SET_LS_PCIE_INFO(info, 1);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE2
|
|
SET_LS_PCIE_INFO(info, 2);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE3
|
|
SET_LS_PCIE_INFO(info, 3);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE4
|
|
SET_LS_PCIE_INFO(info, 4);
|
|
busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
|
|
#endif
|
|
|
|
return busno;
|
|
}
|
|
|
|
void pci_init_board(void)
|
|
{
|
|
ls_pcie_init_board(0);
|
|
}
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
#include <libfdt.h>
|
|
#include <fdt_support.h>
|
|
|
|
static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
|
|
unsigned long ctrl_addr, enum srds_prtcl dev)
|
|
{
|
|
int off;
|
|
|
|
off = fdt_node_offset_by_compat_reg(blob, pci_compat,
|
|
(phys_addr_t)ctrl_addr);
|
|
if (off < 0)
|
|
return;
|
|
|
|
if (!is_serdes_configured(dev))
|
|
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
|
|
}
|
|
|
|
void ft_pci_setup(void *blob, bd_t *bd)
|
|
{
|
|
#ifdef CONFIG_PCIE1
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE2
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE3
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE4
|
|
ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_LSCH3
|
|
fdt_fixup_pcie(blob);
|
|
#endif
|
|
}
|
|
|
|
#else
|
|
void ft_pci_setup(void *blob, bd_t *bd)
|
|
{
|
|
}
|
|
#endif
|