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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
154 lines
4.0 KiB
C
154 lines
4.0 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <s6e63d6.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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return 0;
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}
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int board_early_init_f(void)
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{
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/* CS0: Nor Flash */
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static const struct mxc_weimcs cs0 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0)
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};
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/* CS1: Network Controller */
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static const struct mxc_weimcs cs1 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
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};
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/* CS4: SRAM */
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static const struct mxc_weimcs cs4 = {
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
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CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
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CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
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};
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mxc_setup_weimcs(0, &cs0);
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mxc_setup_weimcs(1, &cs1);
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mxc_setup_weimcs(4, &cs4);
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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/* setup pins for I2C2 (for EEPROM, RTC) */
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mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
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mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_S6E63D6
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struct s6e63d6 data = {
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/*
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* See comment in mxc_spi.c::decode_cs() for .cs field format.
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* We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
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* 2 of the SPI controller #1, since it is unused.
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*/
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.cs = 2 | (57 << 8),
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.bus = 0,
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.id = 0,
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};
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int ret;
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/* SPI1 */
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mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
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mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
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mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
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mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
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mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
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mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
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mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
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/* start SPI1 clock */
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
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/* GPIO 57 */
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/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
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mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
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/* SPI1 CS2 is free */
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ret = s6e63d6_init(&data);
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if (ret)
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return ret;
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/*
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* This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
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* OLED display connected to a S6E63D6 SPI display controller in the
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* 18 bit RGB mode
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*/
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s6e63d6_index(&data, 2);
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s6e63d6_param(&data, 0x0182);
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s6e63d6_index(&data, 3);
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s6e63d6_param(&data, 0x8130);
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s6e63d6_index(&data, 0x10);
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s6e63d6_param(&data, 0x0000);
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s6e63d6_index(&data, 5);
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s6e63d6_param(&data, 0x0001);
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s6e63d6_index(&data, 0x22);
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#endif
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return 0;
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}
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#endif
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int checkboard (void)
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{
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printf("Board: Phytec phyCore i.MX31\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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