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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
200 lines
4.9 KiB
C
200 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
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* Copyright (C) 2016 Grinn
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6ul_pins.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <linux/sizes.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const emmc_pads[] = {
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MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* RST_B */
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MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#ifdef CONFIG_FSL_ESDHC
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static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
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#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
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int litesom_mmc_init(bd_t *bis)
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{
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int ret;
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/* eMMC */
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imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads));
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gpio_direction_output(EMMC_PWR_GPIO, 0);
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udelay(500);
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gpio_direction_output(EMMC_PWR_GPIO, 1);
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emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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ret = fsl_esdhc_initialize(bis, &emmc_cfg);
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if (ret) {
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printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
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return ret;
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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#include <linux/libfdt.h>
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#include <spl.h>
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#include <asm/arch/mx6-ddr.h>
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static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
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.grp_addds = 0x00000030,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_b0ds = 0x00000030,
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.grp_ctlds = 0x00000030,
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.grp_b1ds = 0x00000030,
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.grp_ddrpke = 0x00000000,
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.grp_ddrmode = 0x00020000,
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.grp_ddr_type = 0x000c0000,
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};
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static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
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.dram_dqm0 = 0x00000030,
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.dram_dqm1 = 0x00000030,
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.dram_ras = 0x00000030,
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.dram_cas = 0x00000030,
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.dram_odt0 = 0x00000030,
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.dram_odt1 = 0x00000030,
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.dram_sdba2 = 0x00000000,
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.dram_sdclk_0 = 0x00000030,
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.dram_sdqs0 = 0x00000030,
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.dram_sdqs1 = 0x00000030,
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.dram_reset = 0x00000030,
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};
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static struct mx6_mmdc_calibration mx6_mmcd_calib = {
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.p0_mpwldectrl0 = 0x00000000,
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.p0_mpdgctrl0 = 0x41570155,
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.p0_mprddlctl = 0x4040474A,
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.p0_mpwrdlctl = 0x40405550,
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};
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struct mx6_ddr_sysinfo ddr_sysinfo = {
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.dsize = 0,
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.cs_density = 20,
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.ncs = 1,
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.cs1_mirror = 0,
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.rtt_wr = 2,
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.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
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.walat = 0, /* Write additional latency */
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.ralat = 5, /* Read additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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.bi_on = 1, /* Bank interleaving enabled */
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.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.ddr_type = DDR_TYPE_DDR3,
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.refsel = 0, /* Refresh cycles at 64KHz */
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.refr = 1, /* 2 refresh commands per refresh cycle */
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};
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static struct mx6_ddr3_cfg mem_ddr = {
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.mem_speed = 800,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0xFFFFFFFF, &ccm->CCGR0);
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writel(0xFFFFFFFF, &ccm->CCGR1);
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writel(0xFFFFFFFF, &ccm->CCGR2);
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writel(0xFFFFFFFF, &ccm->CCGR3);
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writel(0xFFFFFFFF, &ccm->CCGR4);
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writel(0xFFFFFFFF, &ccm->CCGR5);
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writel(0xFFFFFFFF, &ccm->CCGR6);
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writel(0xFFFFFFFF, &ccm->CCGR7);
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}
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static void spl_dram_init(void)
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{
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unsigned long ram_size;
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mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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/*
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* Get actual RAM size, so we can adjust DDR row size for <512M
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* memories
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*/
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ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M);
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if (ram_size < SZ_512M) {
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mem_ddr.rowaddr = 14;
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mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
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}
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}
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void litesom_init_f(void)
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{
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ccgr_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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board_early_init_f();
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#endif
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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}
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#endif
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