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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
![Ye Li](/assets/img/avatar_default.png)
Add the board DTS files for 14x14 EVK and 9x9 EVK. They are necessary for converting to use u-boot DM driver. Two -u-boot.dtsi are added to modify compatible string of SPI flash device to "spi-flash". Signed-off-by: Ye Li <ye.li@nxp.com>
472 lines
10 KiB
Plaintext
472 lines
10 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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*/
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/dts-v1/;
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#include "imx6ul.dtsi"
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/ {
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model = "Freescale i.MX6 UltraLite 9x9 EVK Board";
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compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
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aliases {
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spi5 = &soft_spi;
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};
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x80000000 0x20000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_can_3v3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "can-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
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};
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reg_gpio_dvfs: regulator-gpio {
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compatible = "regulator-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dvfs>;
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "gpio_dvfs";
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regulator-type = "voltage";
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gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
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states = <1300000 0x1 1400000 0x0>;
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};
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reg_sd1_vmmc: regulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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off-on-delay = <20000>;
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enable-active-high;
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};
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};
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soft_spi: soft-spi {
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compatible = "spi-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi4>;
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pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
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status = "okay";
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gpio-sck = <&gpio5 11 0>;
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gpio-mosi = <&gpio5 10 0>;
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cs-gpios = <&gpio5 7 0>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio_spi: gpio_spi@0 {
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compatible = "fairchild,74hc595";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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registers-number = <1>;
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registers-default = /bits/ 8 <0x57>;
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spi-max-frequency = <100000>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pmic: pfuze3000@08 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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mag3110@0e {
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compatible = "fsl,mag3110";
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reg = <0x0e>;
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position = <2>;
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};
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fxls8471@1e {
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compatible = "fsl,fxls8471";
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reg = <0x1e>;
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position = <0>;
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interrupt-parent = <&gpio5>;
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interrupts = <0 8>;
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};
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};
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&i2c2 {
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clock_frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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imx6ul-evk {
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pinctrl_dvfs: dvfsgrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
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>;
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};
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
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MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
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MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c1_gpio: i2c1grp_gpio {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
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MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c2_gpio: i2c2grp_gpio {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
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MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
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MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
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MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
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MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
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MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
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MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
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>;
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};
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pinctrl_spi4: spi4grp {
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fsl,pins = <
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MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
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MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
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MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
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MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usb_otg1_id: usbotg1idgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
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>;
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};
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};
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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ddrsmp=<0>;
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flash0: n25q256a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <6>;
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reg = <0>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1_id>;
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dr_mode = "otg";
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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keep-power-in-suspend;
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enable-sdio-wakeup;
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vmmc-supply = <®_sd1_vmmc>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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enable-sdio-wakeup;
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status = "okay";
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};
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&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
};
|